{"id":"https://openalex.org/W3216264835","doi":"https://doi.org/10.1109/isscc.2006.1696060","title":"A Power-Efficient High-Throughput 32-Thread SPARC Processor","display_name":"A Power-Efficient High-Throughput 32-Thread SPARC Processor","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3216264835","doi":"https://doi.org/10.1109/isscc.2006.1696060","mag":"3216264835"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2006.1696060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077447335","display_name":"Ana Sonia Leon","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"A.S. Leon","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054632012","display_name":"Jinuk Luke Shin","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jinuk Luke Shin","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026910611","display_name":"Kam\u2010Weng Tam","orcid":"https://orcid.org/0000-0002-3760-8955"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K.W. Tam","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011600063","display_name":"W. Bryg","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"W. Bryg","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034055199","display_name":"Francis Schumacher","orcid":"https://orcid.org/0009-0004-5112-8941"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. Schumacher","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047515133","display_name":"Poonacha Kongetira","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P. Kongetira","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060910524","display_name":"D. Weisner","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D. Weisner","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046113860","display_name":"A. Strong","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Strong","raw_affiliation_strings":["SUN Mircrosystems, Sunnyvale, CA"],"affiliations":[{"raw_affiliation_string":"SUN Mircrosystems, Sunnyvale, CA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5077447335"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.379,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.97762636,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"295","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7468410134315491},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6823782324790955},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6562900543212891},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.6322770118713379},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.5856057405471802},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5683107376098633},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5496752858161926},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5442254543304443},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4773978292942047},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.41081053018569946},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.37793251872062683},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3714253902435303},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34391671419143677},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.2983805537223816},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29005348682403564},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17300230264663696},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.14897072315216064},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.11845675110816956}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7468410134315491},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6823782324790955},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6562900543212891},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.6322770118713379},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.5856057405471802},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5683107376098633},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5496752858161926},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5442254543304443},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4773978292942047},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.41081053018569946},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.37793251872062683},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3714253902435303},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34391671419143677},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.2983805537223816},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29005348682403564},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17300230264663696},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.14897072315216064},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.11845675110816956},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2006.1696060","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696060","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7300000190734863,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2022740893"],"related_works":["https://openalex.org/W2115561485","https://openalex.org/W1985089255","https://openalex.org/W2153202644","https://openalex.org/W2010970156","https://openalex.org/W2105895556","https://openalex.org/W4235861380","https://openalex.org/W2377593213","https://openalex.org/W2733115356","https://openalex.org/W2106625514","https://openalex.org/W1867214769"],"abstract_inverted_index":{"The":[0,20,40],"first":[1],"generation":[2],"of":[3],"Niagara":[4],"SPARC":[5],"processors":[6],"implements":[7],"a":[8,27,30],"power-efficient":[9],"multi-threading":[10],"architecture":[11],"to":[12,54],"achieve":[13],"high":[14,57],"throughput":[15],"with":[16],"minimum":[17],"hardware":[18],"complexity.":[19],"design":[21,52],"combines":[22],"eight":[23],"4-threaded":[24],"64b":[25],"cores,":[26],"high-bandwidth":[28],"crossbar,":[29],"shared":[31],"3MB":[32],"L2":[33],"Cache":[34],"and":[35],"four":[36],"DDR2":[37],"DRAM":[38],"interfaces.":[39],"90nm":[41],"378mm":[42],"<sup":[43],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[44],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[45],"die":[46],"consumes":[47],"63W":[48],"at":[49],"1.2GHz.":[50],"Memory":[51],"techniques":[53],"support":[55],"the":[56],"bandwidth":[58],"are":[59],"also":[60],"discussed":[61]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}