{"id":"https://openalex.org/W1973152414","doi":"https://doi.org/10.1109/isscc.2006.1696056","title":"A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.","display_name":"A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W1973152414","doi":"https://doi.org/10.1109/isscc.2006.1696056","mag":"1973152414"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2006.1696056","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696056","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089280659","display_name":"Bryan Casper","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Casper","raw_affiliation_strings":["Intel Labs, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090419770","display_name":"James Jaussi","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Jaussi","raw_affiliation_strings":["Intel Labs, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010946517","display_name":"Frank O\u2019Mahony","orcid":"https://orcid.org/0000-0001-7961-9452"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. O'Mahony","raw_affiliation_strings":["Intel Labs, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053540874","display_name":"Mozhgan Mansuri","orcid":"https://orcid.org/0000-0002-0277-7775"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Mansuri","raw_affiliation_strings":["Intel Labs, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058438795","display_name":"K. Canagasaby","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Canagasaby","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113667870","display_name":"James J. Kennedy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Kennedy","raw_affiliation_strings":["Intel Labs, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042245563","display_name":"E. Yeung","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E. Yeung","raw_affiliation_strings":["Intel, Santa Clara, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049783709","display_name":"Randy Mooney","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Mooney","raw_affiliation_strings":["Intel Labs, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"263","last_page":"272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6562627553939819},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.6398727893829346},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6241356134414673},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6048259139060974},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5790924429893494},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5240131616592407},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4996061325073242},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4922901690006256},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.49132099747657776},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.48743584752082825},{"id":"https://openalex.org/keywords/backplane","display_name":"Backplane","score":0.4621354639530182},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.46160808205604553},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.4486437737941742},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4341368079185486},{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.4196809232234955},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32108694314956665},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.2672288417816162},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2575589418411255},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23362714052200317},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2187875509262085},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13696321845054626},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.13075846433639526}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6562627553939819},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.6398727893829346},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6241356134414673},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6048259139060974},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5790924429893494},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5240131616592407},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4996061325073242},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4922901690006256},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.49132099747657776},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.48743584752082825},{"id":"https://openalex.org/C134256836","wikidata":"https://www.wikidata.org/wiki/Q545913","display_name":"Backplane","level":2,"score":0.4621354639530182},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.46160808205604553},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.4486437737941742},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4341368079185486},{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.4196809232234955},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32108694314956665},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.2672288417816162},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2575589418411255},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23362714052200317},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2187875509262085},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13696321845054626},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.13075846433639526},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2006.1696056","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2006.1696056","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2081089490","https://openalex.org/W2150359820"],"related_works":["https://openalex.org/W2567395303","https://openalex.org/W2164893802","https://openalex.org/W1982606279","https://openalex.org/W2359190397","https://openalex.org/W2010754037","https://openalex.org/W2981406251","https://openalex.org/W2170428543","https://openalex.org/W1766742347","https://openalex.org/W2012485143","https://openalex.org/W1973152414"],"abstract_inverted_index":{"Future":[0],"microprocessor":[1],"platforms":[2],"will":[3,94],"require":[4],"system-level":[5,112],"optimization":[6,113],"of":[7,71,80],"the":[8,35,67,78,87],"I/O":[9,36,122],"to":[10,33,85],"minimize":[11,86],"cost":[12,39],"and":[13,25,51,58,61,69,103,133],"maximize":[14,34],"aggregate":[15],"bandwidth.":[16],"Critical":[17],"parameters":[18],"such":[19],"as":[20],"silicon":[21],"area,":[22],"power,":[23],"testability,":[24],"off-chip":[26],"interconnect":[27],"quality":[28,50],"must":[29],"be":[30],"properly":[31],"balanced":[32],"performance":[37],"versus":[38],"ratio.":[40],"For":[41],"example,":[42],"there":[43],"is":[44],"a":[45,62,118,126],"fundamental":[46],"tradeoff":[47],"between":[48],"clock":[49,121],"equalizer":[52],"effectiveness":[53],"[1].":[54],"Producing":[55],"precision":[56],"RX":[57,64],"TX":[59],"clocks":[60],"sensitive":[63],"may":[65],"impact":[66],"power":[68],"area":[70,132],"some":[72],"circuits,":[73],"but":[74],"it":[75],"could":[76],"allow":[77],"use":[79],"simple,":[81],"low-power":[82],"linear":[83],"equalizers":[84,93],"overall":[88],"link":[89,129],"power.":[90,135],"Additionally,":[91],"these":[92],"become":[95],"much":[96],"more":[97],"effective":[98],"by":[99],"limiting":[100],"near-end":[101],"crosstalk":[102],"stubbed":[104],"backplane":[105],"(BP)":[106],"via":[107],"length.":[108],"To":[109],"demonstrate":[110],"this":[111],"effort,":[114],"we":[115],"have":[116],"developed":[117],"20Gb/s":[119],"forwarded":[120],"system":[123],"intended":[124],"for":[125],"wide":[127],"parallel":[128],"with":[130],"small":[131],"low":[134]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}