{"id":"https://openalex.org/W7162693594","doi":"https://doi.org/10.1109/isqed69900.2026.11534654","title":"A Low-overhead Dilithium-NTT Architecture using Accelerated K-RED Modular Reduction Unit","display_name":"A Low-overhead Dilithium-NTT Architecture using Accelerated K-RED Modular Reduction Unit","publication_year":2026,"publication_date":"2026-04-08","ids":{"openalex":"https://openalex.org/W7162693594","doi":"https://doi.org/10.1109/isqed69900.2026.11534654"},"language":null,"primary_location":{"id":"doi:10.1109/isqed69900.2026.11534654","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed69900.2026.11534654","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 27th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101792882","display_name":"H. M. Gupta","orcid":"https://orcid.org/0000-0002-9508-255X"},"institutions":[{"id":"https://openalex.org/I4210148827","display_name":"Birla Institute of Technology and Science, Pilani - Goa Campus","ror":"https://ror.org/046sh6j17","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210148827","https://openalex.org/I74796645"]},{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Harsh Gupta","raw_affiliation_strings":["Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726","institution_ids":["https://openalex.org/I4210148827","https://openalex.org/I74796645"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018639314","display_name":"Aryan Goyal","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148827","display_name":"Birla Institute of Technology and Science, Pilani - Goa Campus","ror":"https://ror.org/046sh6j17","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210148827","https://openalex.org/I74796645"]},{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aryan Goyal","raw_affiliation_strings":["Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726","institution_ids":["https://openalex.org/I4210148827","https://openalex.org/I74796645"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5137231290","display_name":"Paranjay Dhadwal","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148827","display_name":"Birla Institute of Technology and Science, Pilani - Goa Campus","ror":"https://ror.org/046sh6j17","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210148827","https://openalex.org/I74796645"]},{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Paranjay Dhadwal","raw_affiliation_strings":["Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726","institution_ids":["https://openalex.org/I4210148827","https://openalex.org/I74796645"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087628279","display_name":"Jugal Gandhi","orcid":"https://orcid.org/0000-0001-8720-1582"},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jugal Gandhi","raw_affiliation_strings":["CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5137275174","display_name":"Diksha Shekhawat","orcid":null},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Diksha Shekhawat","raw_affiliation_strings":["CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5132596315","display_name":"M. Santosh","orcid":null},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. Santosh","raw_affiliation_strings":["CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011088447","display_name":"Jai Gopal Pandey","orcid":"https://orcid.org/0000-0001-9937-7438"},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jai Gopal Pandey","raw_affiliation_strings":["CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.32280001044273376,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.32280001044273376,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.08980000019073486,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10232","display_name":"Optical Network Technologies","score":0.07580000162124634,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.3910999894142151},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.37450000643730164},{"id":"https://openalex.org/keywords/unit","display_name":"Unit (ring theory)","score":0.3280999958515167},{"id":"https://openalex.org/keywords/work","display_name":"Work (physics)","score":0.29319998621940613},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.2736000120639801},{"id":"https://openalex.org/keywords/control-system","display_name":"Control system","score":0.2727999985218048}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5188000202178955},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.3910999894142151},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.37450000643730164},{"id":"https://openalex.org/C122637931","wikidata":"https://www.wikidata.org/wiki/Q118084","display_name":"Unit (ring theory)","level":2,"score":0.3280999958515167},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31540000438690186},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.2978000044822693},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.29319998621940613},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2736000120639801},{"id":"https://openalex.org/C17500928","wikidata":"https://www.wikidata.org/wiki/Q959968","display_name":"Control system","level":2,"score":0.2727999985218048},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.27059999108314514},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2685999870300293},{"id":"https://openalex.org/C98025372","wikidata":"https://www.wikidata.org/wiki/Q477538","display_name":"Systems architecture","level":3,"score":0.2678999900817871},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.2597000002861023},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.25519999861717224}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed69900.2026.11534654","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed69900.2026.11534654","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 27th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.4916801452636719}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1498685334","https://openalex.org/W2003736153","https://openalex.org/W2084652510","https://openalex.org/W2137147061","https://openalex.org/W2467320551","https://openalex.org/W2791664942","https://openalex.org/W3004368054","https://openalex.org/W3157961299","https://openalex.org/W3159034445","https://openalex.org/W3216234213","https://openalex.org/W3217272717","https://openalex.org/W4210722209","https://openalex.org/W4232836212","https://openalex.org/W4237773356","https://openalex.org/W4293143765","https://openalex.org/W4384947555","https://openalex.org/W4385756739","https://openalex.org/W4387129556","https://openalex.org/W4393406007","https://openalex.org/W4401442713","https://openalex.org/W4411019893","https://openalex.org/W4411725321","https://openalex.org/W4411727094"],"related_works":[],"abstract_inverted_index":{"The":[0,59,92],"increasing":[1],"threat":[2],"posed":[3],"by":[4,26],"quantum":[5],"computers":[6],"to":[7,140],"classical":[8],"cryptographic":[9,16],"systems":[10],"necessitates":[11],"the":[12,35,50,55,63,104,117,128,136,167],"adoption":[13],"of":[14,46,89,152,169],"post-quantum":[15],"(PQC)":[17],"algorithms.":[18],"CRYSTALS-Dilithium,":[19],"a":[20,87,97,131,161],"lattice-based":[21],"digital":[22],"signature":[23],"scheme":[24],"standardized":[25],"NIST,":[27],"relies":[28],"heavily":[29],"on":[30,116],"efficient":[31],"polynomial":[32],"multiplication":[33,52],"using":[34],"number":[36],"theoretic":[37],"transform":[38],"(NTT).":[39],"This":[40],"work":[41],"presents":[42],"an":[43,68,150],"FPGA":[44,125],"implementation":[45],"Dilithium-NTT,":[47],"optimizing":[48],"both":[49],"modular":[51,60],"unit":[53],"and":[54,67,83,122,163],"memory":[56,100],"access":[57,101],"scheme.":[58],"multiplier":[61],"leverages":[62],"data":[64,113],"in":[65,135,172],"LUTs":[66,110],"accelerated":[69],"K-RED":[70],"algorithm,":[71],"achieving":[72],"high":[73],"performance":[74],"with":[75,143,149],"low":[76],"resource":[77],"overhead":[78],"(111":[79],"LUTs,":[80],"137":[81],"FFs,":[82],"02":[84],"DSPs":[85],"at":[86],"frequency":[88],"613":[90],"MHz).":[91],"proposed":[93],"NTT":[94],"architecture":[95],"employs":[96],"dual":[98],"ping-pong":[99],"scheme,":[102],"eliminating":[103],"need":[105],"for":[106,111,166],"BRAMs":[107],"while":[108],"utilizing":[109],"intermediate":[112],"storage.":[114],"Implemented":[115],"Xilinx":[118],"Zynq":[119],"UltraScale+":[120],"ZCU104":[121],"Artix-7":[123],"AC701":[124],"prototyping":[126],"platforms,":[127],"design":[129],"achieves":[130],"$14":[132],"\\%$":[133,145,154],"improvement":[134],"area-time":[137],"product":[138],"compared":[139],"state-of-the-art":[141],"solutions,":[142],"$12":[144],"lower":[146],"LUT":[147],"usage":[148],"advantage":[151],"$6":[153],"higher":[155],"operating":[156],"frequency.":[157],"These":[158],"results":[159],"demonstrate":[160],"scalable":[162],"resource-efficient":[164],"approach":[165],"deployment":[168],"PQC":[170],"primitives":[171],"constrained":[173],"hardware":[174],"environments.":[175]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2026-05-29T00:00:00"}