{"id":"https://openalex.org/W4377969880","doi":"https://doi.org/10.1109/isqed57927.2023.10129290","title":"Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models","display_name":"Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models","publication_year":2023,"publication_date":"2023-04-05","ids":{"openalex":"https://openalex.org/W4377969880","doi":"https://doi.org/10.1109/isqed57927.2023.10129290"},"language":"en","primary_location":{"id":"doi:10.1109/isqed57927.2023.10129290","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/isqed57927.2023.10129290","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037439741","display_name":"Gabriel Barajas","orcid":"https://orcid.org/0000-0002-7955-8722"},"institutions":[{"id":"https://openalex.org/I76308706","display_name":"Microchip Technology (Germany)","ror":"https://ror.org/05bqd9t64","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210093228","https://openalex.org/I76308706"]},{"id":"https://openalex.org/I4210109100","display_name":"Pacific Microchip (United States)","ror":"https://ror.org/01vry7t57","country_code":"US","type":"company","lineage":["https://openalex.org/I4210109100"]}],"countries":["DE","US"],"is_corresponding":true,"raw_author_name":"Gabriel Barajas","raw_affiliation_strings":["Microchip,San Jose,California,USA","Microchip, San Jose, California, USA"],"affiliations":[{"raw_affiliation_string":"Microchip,San Jose,California,USA","institution_ids":["https://openalex.org/I4210109100","https://openalex.org/I76308706"]},{"raw_affiliation_string":"Microchip, San Jose, California, USA","institution_ids":["https://openalex.org/I4210109100"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076157491","display_name":"Jonathan Greene","orcid":"https://orcid.org/0000-0002-7038-6629"},"institutions":[{"id":"https://openalex.org/I4210140627","display_name":"System Biosciences (United States)","ror":"https://ror.org/03583w097","country_code":"US","type":"company","lineage":["https://openalex.org/I4210140627"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan W. Greene","raw_affiliation_strings":["Cambios Computing LLC,Palo Alto,California,USA","Cambios Computing LLC, Palo Alto, California, USA"],"affiliations":[{"raw_affiliation_string":"Cambios Computing LLC,Palo Alto,California,USA","institution_ids":["https://openalex.org/I4210140627"]},{"raw_affiliation_string":"Cambios Computing LLC, Palo Alto, California, USA","institution_ids":["https://openalex.org/I4210140627"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100325808","display_name":"Fei Li","orcid":"https://orcid.org/0000-0002-2870-3010"},"institutions":[{"id":"https://openalex.org/I76308706","display_name":"Microchip Technology (Germany)","ror":"https://ror.org/05bqd9t64","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210093228","https://openalex.org/I76308706"]},{"id":"https://openalex.org/I4210109100","display_name":"Pacific Microchip (United States)","ror":"https://ror.org/01vry7t57","country_code":"US","type":"company","lineage":["https://openalex.org/I4210109100"]}],"countries":["DE","US"],"is_corresponding":false,"raw_author_name":"Fei Li","raw_affiliation_strings":["Microchip,San Jose,California,USA","Microchip, San Jose, California, USA"],"affiliations":[{"raw_affiliation_string":"Microchip,San Jose,California,USA","institution_ids":["https://openalex.org/I4210109100","https://openalex.org/I76308706"]},{"raw_affiliation_string":"Microchip, San Jose, California, USA","institution_ids":["https://openalex.org/I4210109100"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081084989","display_name":"James S. Tandon","orcid":null},"institutions":[{"id":"https://openalex.org/I184813773","display_name":"California State University, East Bay","ror":"https://ror.org/04jaeba88","country_code":"US","type":"education","lineage":["https://openalex.org/I184813773"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James Tandon","raw_affiliation_strings":["California State University East Bay,Hayward,California,USA","California State University East Bay, Hayward, California, USA"],"affiliations":[{"raw_affiliation_string":"California State University East Bay,Hayward,California,USA","institution_ids":["https://openalex.org/I184813773"]},{"raw_affiliation_string":"California State University East Bay, Hayward, California, USA","institution_ids":["https://openalex.org/I184813773"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5037439741"],"corresponding_institution_ids":["https://openalex.org/I4210109100","https://openalex.org/I76308706"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04273058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9050307273864746},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7929338812828064},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.7766153216362},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7140285968780518},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6447043418884277},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.634510338306427},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.5783135294914246},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5213431119918823},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4773257374763489},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.44981130957603455},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.444698303937912},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3923629820346832},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3907039761543274},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.36005714535713196},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3196496367454529},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.25356560945510864},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.22482606768608093},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16907107830047607}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9050307273864746},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7929338812828064},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.7766153216362},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7140285968780518},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6447043418884277},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.634510338306427},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.5783135294914246},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5213431119918823},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4773257374763489},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.44981130957603455},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.444698303937912},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3923629820346832},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3907039761543274},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36005714535713196},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3196496367454529},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.25356560945510864},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22482606768608093},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16907107830047607},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed57927.2023.10129290","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/isqed57927.2023.10129290","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1523051745","https://openalex.org/W1984588379","https://openalex.org/W2030765577","https://openalex.org/W2041053837","https://openalex.org/W2049121968","https://openalex.org/W2095258817","https://openalex.org/W2115310818","https://openalex.org/W2116094656","https://openalex.org/W2163626738","https://openalex.org/W2172215492","https://openalex.org/W2940470334","https://openalex.org/W3003216923","https://openalex.org/W3174010073","https://openalex.org/W6660599780"],"related_works":["https://openalex.org/W2147334865","https://openalex.org/W2164474888","https://openalex.org/W4250005417","https://openalex.org/W2096908507","https://openalex.org/W2123314372","https://openalex.org/W2148701953","https://openalex.org/W2102105233","https://openalex.org/W2057470132","https://openalex.org/W2170665555","https://openalex.org/W2178990935"],"abstract_inverted_index":{"Accurate":[0],"delay":[1,55,111,195],"estimates":[2],"for":[3,16,109,135],"a":[4,9,17,38,46,60,106,116,136],"user":[5],"application":[6],"implemented":[7],"in":[8,45,193],"Field-Programmable":[10],"Gate":[11],"Array":[12],"(FPGA)":[13],"are":[14,196],"essential":[15],"quality":[18],"FPGA":[19,30,84,102],"timing":[20],"flow":[21],"and":[22,79,99,122,159,178],"to":[23,71,172],"avoid":[24],"leaving":[25],"performance":[26],"on":[27,119],"the":[28,75,83,90,110,120,123,127,150,161,179],"table.":[29],"inter-cluster":[31],"routing":[32],"consists":[33],"of":[34,37,41,59,77,89,115,139,164,181,189],"wire":[35,91],"segments":[36],"limited":[39],"number":[40],"types":[42],"which":[43],"repeat":[44],"somewhat":[47],"regular":[48],"pattern,":[49],"interconnected":[50],"by":[51,66,130,198],"configurable":[52],"muxes.":[53],"The":[54],"at":[56,112],"any":[57],"fanout":[58,114],"segment":[61,194],"can":[62],"be":[63,170],"significantly":[64],"impacted":[65],"configuration-dependent":[67],"capacitive":[68],"loading":[69],"related":[70],"other":[72,187],"fanouts.":[73,183],"Also,":[74],"insertion":[76],"RAM":[78],"math":[80],"blocks":[81],"into":[82,149],"floorplan":[85,176],"introduces":[86],"irregular":[87],"stretching":[88],"segments,":[92],"altering":[93],"their":[94],"delays.":[95],"We":[96,141],"explain":[97],"why":[98],"how":[100],"commercial":[101],"software":[103],"typically":[104],"employs":[105],"parameterized":[107],"model":[108],"each":[113],"segment,":[117],"based":[118],"configuration":[121],"irregularities":[124,177],"present,":[125],"with":[126,156,186],"parameters":[128,158],"determined":[129],"fitting":[131],"SPICE":[132,165],"simulation":[133],"data":[134,166],"representative":[137],"sample":[138],"cases.":[140],"propose":[142],"incorporating":[143],"readily-computed":[144],"common":[145],"path":[146],"resistance":[147],"values":[148],"model.":[151],"This":[152],"enables":[153],"high":[154],"accuracy":[155],"fewer":[157],"without":[160],"large":[162],"amounts":[163],"that":[167],"would":[168],"otherwise":[169],"required":[171],"explore":[173],"interactions":[174],"between":[175],"set":[180],"active":[182],"In":[184],"combination":[185],"features":[188],"our":[190],"models,":[191],"errors":[192],"reduced":[197],"almost":[199],"half.":[200]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}