{"id":"https://openalex.org/W4283696245","doi":"https://doi.org/10.1109/isqed54688.2022.9806140","title":"Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary Algorithm","display_name":"Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary Algorithm","publication_year":2022,"publication_date":"2022-04-06","ids":{"openalex":"https://openalex.org/W4283696245","doi":"https://doi.org/10.1109/isqed54688.2022.9806140"},"language":"en","primary_location":{"id":"doi:10.1109/isqed54688.2022.9806140","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed54688.2022.9806140","pdf_url":null,"source":{"id":"https://openalex.org/S4363607671","display_name":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069844816","display_name":"Rabin Yu Acharya","orcid":"https://orcid.org/0000-0001-5952-4093"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rabin Yu Acharya","raw_affiliation_strings":["University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009243659","display_name":"Domenic Forte","orcid":"https://orcid.org/0000-0002-2794-7320"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Domenic Forte","raw_affiliation_strings":["University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Florida,Department of Electrical and Computer Engineering,Gainesville,FL,USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05923695,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6488499641418457},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5512998700141907},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5033263564109802},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4907306432723999},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.48758143186569214},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4688606858253479},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4634961783885956},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43580326437950134},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3498079776763916},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34786051511764526},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3387465178966522},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23159745335578918},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1551252007484436}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6488499641418457},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5512998700141907},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5033263564109802},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4907306432723999},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.48758143186569214},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4688606858253479},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4634961783885956},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43580326437950134},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3498079776763916},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34786051511764526},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3387465178966522},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23159745335578918},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1551252007484436},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed54688.2022.9806140","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed54688.2022.9806140","pdf_url":null,"source":{"id":"https://openalex.org/S4363607671","display_name":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W42037993","https://openalex.org/W1490907850","https://openalex.org/W2000171858","https://openalex.org/W2002734120","https://openalex.org/W2005868100","https://openalex.org/W2067907366","https://openalex.org/W2116359098","https://openalex.org/W2117299791","https://openalex.org/W2126105956","https://openalex.org/W2133585063","https://openalex.org/W2169366198","https://openalex.org/W2198098822","https://openalex.org/W2502734849","https://openalex.org/W2791198567","https://openalex.org/W2914764075","https://openalex.org/W2985307378","https://openalex.org/W3021613070","https://openalex.org/W3047031678","https://openalex.org/W3124645152","https://openalex.org/W3198389916","https://openalex.org/W6789525128"],"related_works":["https://openalex.org/W1980349267","https://openalex.org/W2098419840","https://openalex.org/W2140610743","https://openalex.org/W2116326546","https://openalex.org/W2097637358","https://openalex.org/W2151104031","https://openalex.org/W2765435638","https://openalex.org/W2766377030","https://openalex.org/W1974416117","https://openalex.org/W2168458994"],"abstract_inverted_index":{"Physically":[0],"unclonable":[1],"functions":[2],"(PUFs)":[3],"are":[4,83,181],"hardware":[5,13],"security":[6],"primitives":[7],"which":[8,165],"can":[9],"be":[10],"used":[11],"for":[12,35,54,76,121,159],"authentication":[14],"and":[15,99,108,116,124,200],"cryptographic":[16],"key":[17],"generation.":[18],"The":[19],"design":[20,26,47,63,69,101,113,131],"of":[21,27,48,62,70,85,132,148,161,197,220],"PUFs":[22,71],"involves":[23],"configuring":[24],"the":[25,40,46,68,86,130,162,218],"existing":[28],"cells":[29],"within":[30],"an":[31],"integrated":[32],"circuit":[33,42,50,90,119,189],"(IC)":[34],"PUF":[36,49,118,139,164,173,188],"operation":[37],"without":[38],"impacting":[39],"normal":[41],"operation.":[43],"This":[44],"makes":[45],"very":[51],"challenging":[52],"especially":[53],"analog":[55,81,123],"circuits":[56,78],"as":[57,145],"they":[58],"have":[59],"higher":[60,191],"number":[61],"specifications":[64],"to":[65,112,168,183,206,216],"meet.":[66],"Thus,":[67],"has":[72],"been":[73],"explored":[74,153],"mainly":[75],"digital":[77,125],"even":[79],"though":[80],"ICs":[82],"one":[84],"most":[87],"highly":[88,171],"counterfeited":[89],"types.":[91],"In":[92,177],"this":[93,178],"paper,":[94],"we":[95,128,180],"present":[96,129],"a":[97,114,146,154,170,185,194],"clear":[98],"straightforward":[100],"methodology":[102],"that":[103,140],"includes":[104],"automated":[105],"frequency-based":[106],"analysis":[107],"evolutionary":[109,212],"algorithm-based":[110],"optimization":[111,158],"robust":[115,187],"reliable":[117],"suitable":[120],"both":[122],"circuits.":[126],"Specifically,":[127],"null":[133],"conventional":[134],"logic":[135],"gate":[136],"based":[137,157,214],"(NCL)":[138],"exploits":[141],"its":[142],"startup":[143],"characteristics":[144],"source":[147],"entropy.":[149],"Our":[150],"previous":[151],"work":[152],"delay":[155],"matching":[156],"transistors":[160],"NCL":[163],"was":[166],"able":[167,182],"obtain":[169,184],"unique":[172],"with":[174,190],"fair":[175],"reliability.":[176],"work,":[179],"more":[186],"reliability":[192],"across":[193],"wide":[195],"range":[196],"temperature":[198],"(0\u00b0C-120\u00b0C)":[199],"supply":[201],"voltage":[202],"variations":[203],"(of":[204],"up":[205],"\u00b110%).":[207],"We":[208],"also":[209],"compare":[210],"different":[211],"algorithm":[213],"techniques":[215],"demonstrate":[217],"effectiveness":[219],"our":[221],"proposed":[222],"methodology.":[223]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}