{"id":"https://openalex.org/W3163261102","doi":"https://doi.org/10.1109/isqed51717.2021.9424352","title":"Global Multi-voltage Interface Unit for Diverse Digital Logic","display_name":"Global Multi-voltage Interface Unit for Diverse Digital Logic","publication_year":2021,"publication_date":"2021-04-07","ids":{"openalex":"https://openalex.org/W3163261102","doi":"https://doi.org/10.1109/isqed51717.2021.9424352","mag":"3163261102"},"language":"en","primary_location":{"id":"doi:10.1109/isqed51717.2021.9424352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed51717.2021.9424352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068652014","display_name":"Naranamangalam Balaji Prashanth","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"N Prashanth","raw_affiliation_strings":["Intel Corporation, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027333139","display_name":"Manisha Girish","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Manisha Girish","raw_affiliation_strings":["Intel Corporation, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084120695","display_name":"Sandeep Motebennur","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sandeep Motebennur","raw_affiliation_strings":["Intel Corporation, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009612147","display_name":"K M Prasanna","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Krishna Prasanna","raw_affiliation_strings":["Intel Corporation, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081462178","display_name":"Karthik Suman","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Karthik Suman","raw_affiliation_strings":["Intel Corporation, India"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, India","institution_ids":["https://openalex.org/I4210146682"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5068652014"],"corresponding_institution_ids":["https://openalex.org/I4210146682"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04297493,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"307","last_page":"307"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6565961241722107},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.642754852771759},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5557095408439636},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.523813784122467},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.47479337453842163},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4608999490737915},{"id":"https://openalex.org/keywords/isolation","display_name":"Isolation (microbiology)","score":0.4456758499145508},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4397607445716858},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42651262879371643},{"id":"https://openalex.org/keywords/cpu-core-voltage","display_name":"CPU core voltage","score":0.42570197582244873},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4017254114151001},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3428899049758911},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3254585862159729},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3173424005508423},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24129849672317505},{"id":"https://openalex.org/keywords/voltage-droop","display_name":"Voltage droop","score":0.2212207019329071},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.11016890406608582}],"concepts":[{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6565961241722107},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.642754852771759},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5557095408439636},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.523813784122467},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.47479337453842163},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4608999490737915},{"id":"https://openalex.org/C2775941552","wikidata":"https://www.wikidata.org/wiki/Q25212305","display_name":"Isolation (microbiology)","level":2,"score":0.4456758499145508},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4397607445716858},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42651262879371643},{"id":"https://openalex.org/C55038917","wikidata":"https://www.wikidata.org/wiki/Q453979","display_name":"CPU core voltage","level":5,"score":0.42570197582244873},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4017254114151001},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3428899049758911},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3254585862159729},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3173424005508423},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24129849672317505},{"id":"https://openalex.org/C40760162","wikidata":"https://www.wikidata.org/wiki/Q10920295","display_name":"Voltage droop","level":4,"score":0.2212207019329071},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.11016890406608582},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C89423630","wikidata":"https://www.wikidata.org/wiki/Q7193","display_name":"Microbiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed51717.2021.9424352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed51717.2021.9424352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2163835931","https://openalex.org/W2166243422"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2114346412","https://openalex.org/W2098419840","https://openalex.org/W3023368799","https://openalex.org/W2580743037","https://openalex.org/W1966764473","https://openalex.org/W2116516992","https://openalex.org/W2102826383","https://openalex.org/W1558283416","https://openalex.org/W2766377030"],"abstract_inverted_index":{"In":[0],"the":[1,58],"development":[2],"of":[3],"low":[4],"power":[5],"SoCs,":[6],"multi-voltage":[7,32,99],"designs":[8,100],"are":[9],"most":[10,39],"preferred":[11],"options":[12],"due":[13,25],"to":[14,26,96,98],"various":[15],"reasons.":[16],"Front":[17],"end":[18],"design":[19,54,63],"methodologies":[20],"often":[21],"face":[22],"many":[23],"challenges":[24],"multiple":[27],"IPs/Design":[28],"units":[29],"residing":[30],"on":[31],"domains":[33],"in":[34,38],"SoCs.":[35],"Design":[36],"convergence":[37],"cases,":[40],"need":[41],"frequent":[42],"updates":[43],"distributed":[44],"across":[45],"physical":[46],"and":[47,65,101],"logical":[48],"partitions.":[49],"This":[50],"poses":[51],"difficulties":[52],"for":[53,89],"closure":[55],"especially":[56],"at":[57],"final":[59],"stages.":[60],"To":[61],"minimize":[62],"efforts":[64],"cost,":[66],"a":[67],"global":[68],"interface":[69,81],"unit,":[70],"which":[71],"can":[72,83],"house":[73,84],"diverse":[74],"digital":[75],"logic,":[76],"is":[77],"implemented.":[78],"The":[79],"proposed":[80],"unit":[82],"level-shifters,":[85],"isolation":[86],"cells,":[87],"buffers":[88],"signal":[90],"splitting,":[91],"repeaters,":[92],"glue":[93],"logic":[94],"etc.,":[95],"cater":[97],"faster":[102],"convergence.":[103]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
