{"id":"https://openalex.org/W3163319054","doi":"https://doi.org/10.1109/isqed51717.2021.9424350","title":"A Comprehensive Multi-Voltage Design Platform for System-Level Validation of Standard Cell Library","display_name":"A Comprehensive Multi-Voltage Design Platform for System-Level Validation of Standard Cell Library","publication_year":2021,"publication_date":"2021-04-07","ids":{"openalex":"https://openalex.org/W3163319054","doi":"https://doi.org/10.1109/isqed51717.2021.9424350","mag":"3163319054"},"language":"en","primary_location":{"id":"doi:10.1109/isqed51717.2021.9424350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed51717.2021.9424350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112655720","display_name":"Akshay Kamath","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139030","display_name":"Samsung (India)","ror":"https://ror.org/04cpx2569","country_code":"IN","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210139030"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Akshay Kamath","raw_affiliation_strings":["Samsung Semiconductor India R&D Center, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Samsung Semiconductor India R&D Center, Bengaluru, India","institution_ids":["https://openalex.org/I4210139030"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060469350","display_name":"Bharath Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139030","display_name":"Samsung (India)","ror":"https://ror.org/04cpx2569","country_code":"IN","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210139030"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bharath Kumar","raw_affiliation_strings":["Samsung Semiconductor India R&D Center, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Samsung Semiconductor India R&D Center, Bengaluru, India","institution_ids":["https://openalex.org/I4210139030"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111059263","display_name":"Sunil Aggarwal","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139030","display_name":"Samsung (India)","ror":"https://ror.org/04cpx2569","country_code":"IN","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210139030"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sunil Aggarwal","raw_affiliation_strings":["Samsung Semiconductor India R&D Center, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Samsung Semiconductor India R&D Center, Bengaluru, India","institution_ids":["https://openalex.org/I4210139030"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041100143","display_name":"Subramanian Parameswaran","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139030","display_name":"Samsung (India)","ror":"https://ror.org/04cpx2569","country_code":"IN","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210139030"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Subramanian Parameswaran","raw_affiliation_strings":["Samsung Semiconductor India R&D Center, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Samsung Semiconductor India R&D Center, Bengaluru, India","institution_ids":["https://openalex.org/I4210139030"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036844970","display_name":"Mitesh Goyal","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139030","display_name":"Samsung (India)","ror":"https://ror.org/04cpx2569","country_code":"IN","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210139030"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mitesh Goyal","raw_affiliation_strings":["Samsung Semiconductor India R&D Center, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Samsung Semiconductor India R&D Center, Bengaluru, India","institution_ids":["https://openalex.org/I4210139030"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032594288","display_name":"Parag Lonkar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139030","display_name":"Samsung (India)","ror":"https://ror.org/04cpx2569","country_code":"IN","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210139030"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Parag Lonkar","raw_affiliation_strings":["Samsung Semiconductor India R&D Center, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Samsung Semiconductor India R&D Center, Bengaluru, India","institution_ids":["https://openalex.org/I4210139030"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020755191","display_name":"Somasunder Sreenath","orcid":null},"institutions":[{"id":"https://openalex.org/I4210139030","display_name":"Samsung (India)","ror":"https://ror.org/04cpx2569","country_code":"IN","type":"company","lineage":["https://openalex.org/I2250650973","https://openalex.org/I4210139030"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Somasunder Sreenath","raw_affiliation_strings":["Samsung Semiconductor India R&D Center, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Samsung Semiconductor India R&D Center, Bengaluru, India","institution_ids":["https://openalex.org/I4210139030"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5112655720"],"corresponding_institution_ids":["https://openalex.org/I4210139030"],"apc_list":null,"apc_paid":null,"fwci":0.1003,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.40812486,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"285","last_page":"291"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.7991354465484619},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6897547245025635},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6743609309196472},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6168742775917053},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.5915239453315735},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.556686282157898},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5255928039550781},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4496475160121918},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2128371000289917},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.15470096468925476}],"concepts":[{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.7991354465484619},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6897547245025635},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6743609309196472},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6168742775917053},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.5915239453315735},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.556686282157898},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5255928039550781},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4496475160121918},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2128371000289917},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.15470096468925476},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed51717.2021.9424350","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed51717.2021.9424350","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1940169316","https://openalex.org/W2147889306","https://openalex.org/W2150691261","https://openalex.org/W2534136824","https://openalex.org/W6728354216"],"related_works":["https://openalex.org/W4288055011","https://openalex.org/W2100360214","https://openalex.org/W3209275736","https://openalex.org/W2889102485","https://openalex.org/W2031041696","https://openalex.org/W2388299947","https://openalex.org/W4242912623","https://openalex.org/W2134697552","https://openalex.org/W4385831984","https://openalex.org/W2110396545"],"abstract_inverted_index":{"The":[0,155],"quality":[1,189],"assurance":[2],"checks":[3],"for":[4],"standard":[5,43,61,111,143,191],"cell":[6,62,192],"libraries":[7],"are":[8,45,52],"generally":[9],"limited":[10],"to":[11,91,163,173],"validation":[12,176],"at":[13,67],"individual":[14],"cell-level.":[15],"In":[16],"complex":[17],"custom":[18],"ASIC":[19],"designs":[20],"such":[21],"as":[22],"system-on-chips,":[23],"which":[24,106,167],"comprise":[25],"of":[26,42,110,121,138,141,145,182,190],"multiple":[27],"voltage":[28],"island":[29],"and":[30,118,127,161],"power":[31],"domain":[32],"blocks":[33],"communicating":[34],"over":[35],"shared":[36],"bus":[37],"interconnects,":[38],"the":[39,48,60,80,85,93,108,135,179,187],"operating":[40],"conditions":[41],"cells":[44,112,144],"different":[46,164],"from":[47],"discrete":[49],"environment":[50,117],"they":[51],"tested":[53],"in.":[54],"Consequently,":[55],"any":[56],"design":[57,104,132,156],"bugs":[58],"in":[59,75,113,149],"library":[63,89,148,183],"that":[64],"go":[65],"undetected":[66],"cell-level":[68],"but":[69],"get":[70],"captured":[71],"during":[72,178],"their":[73,122],"usage":[74,109],"chip":[76],"development":[77],"adversely":[78],"affects":[79],"time-to-market":[81],"while":[82],"also":[83],"increasing":[84],"resource":[86],"requirement":[87],"on":[88],"designers":[90],"resolve":[92],"identified":[94],"issues.":[95],"To":[96],"bridge":[97],"this":[98],"gap,":[99],"we":[100],"introduce":[101],"a":[102,114,146,150,170],"comprehensive":[103],"framework":[105],"emulates":[107],"multi-voltage":[115],"system-level":[116,175],"facilitates":[119],"testing":[120],"use-case":[123],"correctness":[124],"through":[125],"functional":[126],"low-power":[128],"simulation":[129],"checks.":[130],"Our":[131],"approach":[133],"provides":[134],"distinct":[136],"advantage":[137],"100%":[139],"coverage":[140],"logical":[142],"given":[147],"single":[151],"poweraware":[152],"gate-level":[153],"netlist.":[154],"infrastructure":[157],"is":[158],"highly":[159],"automated":[160],"scalable":[162],"technology":[165],"nodes":[166],"makes":[168],"it":[169],"powerful":[171],"platform":[172],"build":[174],"flows":[177],"early":[180],"stages":[181],"development,":[184],"thereby":[185],"improving":[186],"overall":[188],"libraries.":[193]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}