{"id":"https://openalex.org/W3162376523","doi":"https://doi.org/10.1109/isqed51717.2021.9424338","title":"Automatic Generation of Translators for Packet-Based and Emerging Protocols","display_name":"Automatic Generation of Translators for Packet-Based and Emerging Protocols","publication_year":2021,"publication_date":"2021-04-07","ids":{"openalex":"https://openalex.org/W3162376523","doi":"https://doi.org/10.1109/isqed51717.2021.9424338","mag":"3162376523"},"language":"en","primary_location":{"id":"doi:10.1109/isqed51717.2021.9424338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed51717.2021.9424338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089938000","display_name":"Brian Crafton","orcid":"https://orcid.org/0000-0002-0227-0421"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Brian Crafton","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091408102","display_name":"Arijit Raychowdhury","orcid":"https://orcid.org/0000-0001-8391-0576"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arijit Raychowdhury","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung-Kyu Lim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5089938000"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06137583,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"488","last_page":"495"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8504999279975891},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.5854256749153137},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.5635126233100891},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5385661125183105},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5239137411117554},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.4810386002063751},{"id":"https://openalex.org/keywords/standardization","display_name":"Standardization","score":0.46618008613586426},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.45583558082580566},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.4516826570034027},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4285026490688324},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4230736792087555},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3865766227245331},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3597414493560791},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2708108127117157},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25427401065826416},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.22330841422080994}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8504999279975891},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5854256749153137},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.5635126233100891},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5385661125183105},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5239137411117554},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.4810386002063751},{"id":"https://openalex.org/C188087704","wikidata":"https://www.wikidata.org/wiki/Q369577","display_name":"Standardization","level":2,"score":0.46618008613586426},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.45583558082580566},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.4516826570034027},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4285026490688324},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4230736792087555},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3865766227245331},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3597414493560791},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2708108127117157},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25427401065826416},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.22330841422080994},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed51717.2021.9424338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed51717.2021.9424338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1518895841","https://openalex.org/W1523401229","https://openalex.org/W2047314385","https://openalex.org/W2079653380","https://openalex.org/W2091528902","https://openalex.org/W2097913124","https://openalex.org/W2123184444","https://openalex.org/W2125551870","https://openalex.org/W2130688260","https://openalex.org/W2153829097","https://openalex.org/W2945577986","https://openalex.org/W2983806215","https://openalex.org/W3011338798","https://openalex.org/W3015690986","https://openalex.org/W3016212306","https://openalex.org/W6762975982","https://openalex.org/W6770156513"],"related_works":["https://openalex.org/W2378767206","https://openalex.org/W1540871478","https://openalex.org/W1937259677","https://openalex.org/W2364820253","https://openalex.org/W2366672283","https://openalex.org/W2385469434","https://openalex.org/W2972757702","https://openalex.org/W2378068131","https://openalex.org/W2382248211","https://openalex.org/W4295713093"],"abstract_inverted_index":{"A":[0],"recent":[1],"trend":[2],"in":[3,44],"open":[4,50],"source":[5,51],"hardware":[6,36],"and":[7,21,95,127,137],"chipletbased":[8],"IP":[9,39,67],"reuse":[10],"faces":[11],"a":[12,26,41,46,59,70,102,110],"key":[13],"obstacle:":[14],"protocol":[15,71,141],"standardization.":[16],"Hardware":[17],"interfaces":[18,37],"lack":[19],"flexibility":[20],"require":[22],"designers":[23],"to":[24,61,93],"follow":[25],"strict":[27],"behavior":[28],"when":[29],"implementing":[30],"IP.":[31,52],"The":[32],"rigid":[33],"nature":[34],"of":[35,48],"prevents":[38],"reuse,":[40],"critical":[42],"challenge":[43],"integrating":[45],"plethora":[47],"emerging":[49],"To":[53],"mitigate":[54],"these":[55,99],"challenges,":[56],"we":[57,75,90,117],"propose":[58],"tool":[60],"automatically":[62],"synthesize":[63],"translators":[64],"between":[65,98,112],"arbitrary":[66],"blocks.":[68],"Using":[69],"description":[72],"language":[73],"(PDL),":[74],"model":[76],"protocols":[77],"such":[78],"that":[79],"they":[80],"can":[81],"be":[82],"interpreted":[83],"as":[84,109],"finite":[85],"state":[86,105,121],"machines":[87],"(FSM).":[88],"Next,":[89],"design":[91],"algorithms":[92],"map":[94],"schedule":[96],"transactions":[97],"protocols,":[100],"generating":[101],"single":[103],"integrated":[104,120],"machine":[106,122],"which":[107],"serves":[108],"translator":[111],"the":[113],"two":[114],"protocols.":[115],"Lastly,":[116],"convert":[118],"our":[119],"into":[123],"readable":[124],"RTL":[125],"(Verilog)":[126],"perform":[128],"functional":[129],"verification.":[130],"Our":[131],"flow":[132],"has":[133],"been":[134],"implemented,":[135],"tested,":[136],"proven":[138],"on":[139],"12":[140],"pairs":[142],"with":[143],"unique":[144],"behavior.":[145]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}