{"id":"https://openalex.org/W3041149751","doi":"https://doi.org/10.1109/isqed48828.2020.9137032","title":"Two-Graph Approach to Temperature Dependent Skew Scheduling","display_name":"Two-Graph Approach to Temperature Dependent Skew Scheduling","publication_year":2020,"publication_date":"2020-03-01","ids":{"openalex":"https://openalex.org/W3041149751","doi":"https://doi.org/10.1109/isqed48828.2020.9137032","mag":"3041149751"},"language":"en","primary_location":{"id":"doi:10.1109/isqed48828.2020.9137032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed48828.2020.9137032","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112420841","display_name":"Mineo Kaneko","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Mineo Kaneko","raw_affiliation_strings":["School of Information Science, Japan Advanced Institute of Science and Technology, 1\u20131 Asahidai, Nomi-shi, Ishikawa, Japan"],"affiliations":[{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology, 1\u20131 Asahidai, Nomi-shi, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5112420841"],"corresponding_institution_ids":["https://openalex.org/I177738480"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05934318,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"432","last_page":"437"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7983678579330444},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.5899779796600342},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5355605483055115},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5203911066055298},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.5142931342124939},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.48529452085494995},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.43856891989707947},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4299051761627197},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4021662473678589},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4010370671749115},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.2963314354419708},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.26402950286865234},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.26321840286254883},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.16699880361557007},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.1478666067123413},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13152354955673218},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0986175537109375}],"concepts":[{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7983678579330444},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5899779796600342},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5355605483055115},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5203911066055298},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.5142931342124939},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.48529452085494995},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.43856891989707947},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4299051761627197},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4021662473678589},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4010370671749115},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.2963314354419708},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.26402950286865234},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.26321840286254883},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.16699880361557007},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.1478666067123413},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13152354955673218},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0986175537109375},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed48828.2020.9137032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed48828.2020.9137032","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1511469799","https://openalex.org/W2080438712","https://openalex.org/W2136006926","https://openalex.org/W2141923369","https://openalex.org/W2157133114","https://openalex.org/W2160913524","https://openalex.org/W2167945639","https://openalex.org/W2171658874","https://openalex.org/W3172772885","https://openalex.org/W4230763194","https://openalex.org/W4238535529","https://openalex.org/W6684845481","https://openalex.org/W6797258325"],"related_works":["https://openalex.org/W2116259070","https://openalex.org/W2163318442","https://openalex.org/W2123512677","https://openalex.org/W2011677428","https://openalex.org/W2128528443","https://openalex.org/W4232019485","https://openalex.org/W4327499872","https://openalex.org/W2164834710","https://openalex.org/W2028052815","https://openalex.org/W2066822161"],"abstract_inverted_index":{"Temperature":[0],"is":[1,27,53,73,85],"one":[2],"of":[3,7,22,41,61,101,112,116,125,128,132],"the":[4,33,46,96,99,104,110,113,123],"major":[5],"sources":[6],"delay":[8,49],"variability":[9],"which":[10,59],"may":[11],"cause":[12],"timing":[13],"violations.":[14],"In":[15],"this":[16],"paper,":[17],"a":[18,42,56,78,89,138],"novel":[19],"design":[20],"method":[21],"temperature":[23,38,47,114,129],"dependent":[24,48,130],"intentional":[25,117,146],"skew":[26,102],"proposed":[28],"in":[29,137],"order":[30],"to":[31],"improve":[32],"performances":[34],"(clock":[35],"frequency,":[36],"operating":[37,81],"range,":[39],"etc.)":[40],"sequential":[43],"circuit":[44,140],"under":[45],"variability.":[50],"Our":[51,119],"approach":[52,120],"based":[54],"on":[55],"constraint":[57],"graph":[58],"consists":[60],"two":[62,69],"subgraphs":[63],"and":[64,92,106,141],"edges":[65,94],"for":[66,74,86,145],"bridging":[67,93],"these":[68],"subgraphs.":[70],"One":[71],"subgraph":[72,84],"representing":[75],"constraints":[76,87],"at":[77,88,103],"specified":[79],"low-end":[80,105],"temperature,":[82,91],"another":[83],"high-end":[90,107],"constrain":[95],"relation":[97],"between":[98],"amounts":[100],"temperatures":[108],"reflecting":[109],"characteristics":[111],"dependency":[115],"skews.":[118,147],"can":[121],"handle":[122],"mixture":[124],"various":[126],"types":[127],"delays":[131,136,144],"both":[133],"signal":[134],"propagation":[135,143],"combinatorial":[139],"clock":[142]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
