{"id":"https://openalex.org/W2802158532","doi":"https://doi.org/10.1109/isqed.2018.8357278","title":"Network on interconnect fabric","display_name":"Network on interconnect fabric","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2802158532","doi":"https://doi.org/10.1109/isqed.2018.8357278","mag":"2802158532"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2018.8357278","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2018.8357278","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://escholarship.org/content/qt6964s32s/qt6964s32s.pdf?t=pj5x3l","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064794690","display_name":"Boris Vaisband","orcid":"https://orcid.org/0000-0002-6176-5918"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Boris Vaisband","raw_affiliation_strings":["Department of Electrical and Computer Engineering University of California, Center for Heterogeneous Integration and Performance Scaling (CHIPS), Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering University of California, Center for Heterogeneous Integration and Performance Scaling (CHIPS), Los Angeles, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078908420","display_name":"Adeel Bajwa","orcid":"https://orcid.org/0000-0003-1007-7944"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Adeel Bajwa","raw_affiliation_strings":["Department of Electrical and Computer Engineering University of California, Center for Heterogeneous Integration and Performance Scaling (CHIPS), Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering University of California, Center for Heterogeneous Integration and Performance Scaling (CHIPS), Los Angeles, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091022757","display_name":"Subramanian S. Iyer","orcid":"https://orcid.org/0000-0003-1220-031X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Subramanian S. Iyer","raw_affiliation_strings":["Department of Electrical and Computer Engineering University of California, Center for Heterogeneous Integration and Performance Scaling (CHIPS), Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering University of California, Center for Heterogeneous Integration and Performance Scaling (CHIPS), Los Angeles, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5064794690"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9768,"has_fulltext":true,"cited_by_count":11,"citation_normalized_percentile":{"value":0.78474882,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"138","last_page":"143"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8316594362258911},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6338618993759155},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.5511658787727356},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5418781042098999},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4980299472808838},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.42892590165138245},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4085581302642822},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3860950469970703},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29524779319763184},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2913568615913391},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.19481921195983887},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1874440610408783},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.11476033926010132}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8316594362258911},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6338618993759155},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.5511658787727356},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5418781042098999},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4980299472808838},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.42892590165138245},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4085581302642822},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3860950469970703},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29524779319763184},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2913568615913391},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.19481921195983887},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1874440610408783},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.11476033926010132},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/isqed.2018.8357278","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2018.8357278","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},{"id":"pmh:qt6964s32s","is_oa":true,"landing_page_url":"http://www.escholarship.org/uc/item/6964s32s","pdf_url":"https://escholarship.org/content/qt6964s32s/qt6964s32s.pdf?t=pj5x3l","source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Vaisband, Boris; Bajwa, Adeel; & Iyer, Subramanian. (2018). Network on Interconnect Fabric. Proceedings of the IEEE International Symposium on Quality Electronic Design. UCLA: Retrieved from: http://www.escholarship.org/uc/item/6964s32s","raw_type":"article"},{"id":"pmh:oai:escholarship.org/ark:/13030/qt6964s32s","is_oa":false,"landing_page_url":"https://escholarship.org/uc/item/6964s32s","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"}],"best_oa_location":{"id":"pmh:qt6964s32s","is_oa":true,"landing_page_url":"http://www.escholarship.org/uc/item/6964s32s","pdf_url":"https://escholarship.org/content/qt6964s32s/qt6964s32s.pdf?t=pj5x3l","source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Vaisband, Boris; Bajwa, Adeel; & Iyer, Subramanian. (2018). Network on Interconnect Fabric. Proceedings of the IEEE International Symposium on Quality Electronic Design. UCLA: Retrieved from: http://www.escholarship.org/uc/item/6964s32s","raw_type":"article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2802158532.pdf","grobid_xml":"https://content.openalex.org/works/W2802158532.grobid-xml"},"referenced_works_count":20,"referenced_works":["https://openalex.org/W208686736","https://openalex.org/W1543543752","https://openalex.org/W2027240837","https://openalex.org/W2029279820","https://openalex.org/W2109125995","https://openalex.org/W2119677480","https://openalex.org/W2124009478","https://openalex.org/W2136369255","https://openalex.org/W2155461249","https://openalex.org/W2220248802","https://openalex.org/W2296539640","https://openalex.org/W2320552075","https://openalex.org/W2482450555","https://openalex.org/W2525693606","https://openalex.org/W2543533520","https://openalex.org/W2553513600","https://openalex.org/W2742519254","https://openalex.org/W2745282586","https://openalex.org/W2781654239","https://openalex.org/W3199229526"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2112235696","https://openalex.org/W1511998565","https://openalex.org/W2160129109","https://openalex.org/W2615259895","https://openalex.org/W2013237228","https://openalex.org/W4231453522","https://openalex.org/W1984658281","https://openalex.org/W2103733668","https://openalex.org/W2099977505"],"abstract_inverted_index":{"Silicon":[0],"interconnect":[1,41],"fabric":[2,42],"(Si-IF)":[3],"supports":[4],"integration":[5,52],"of":[6,53,96],"bare":[7],"dies":[8,70],"using":[9,33],"thermal":[10],"compression":[11],"bonding":[12],"on":[13,40,68],"a":[14],"Si":[15,35],"wafer":[16],"substrate.":[17],"Fine":[18],"pitch":[19],"(2":[20],"to":[21],"10":[22],"\u03bcm)":[23],"horizontal":[24],"and":[25,85,89,94,99,102],"vertical":[26],"inter-connects":[27],"are":[28],"feasible":[29],"within":[30,59,76],"the":[31,60,77,97,100],"Si-IF":[32,63],"standard":[34],"processing":[36,88],"techniques.":[37],"A":[38],"network":[39],"(NoIF)":[43],"is":[44,66],"proposed":[45],"in":[46],"this":[47],"paper.":[48],"The":[49],"NoIF":[50,65,79],"enables":[51,80],"ultra":[54],"large":[55],"scale":[56],"heterogeneous":[57],"systems":[58],"technologically":[61],"mature":[62],"platform.":[64],"based":[67],"utility":[69,101],"which":[71],"serve":[72],"as":[73],"intelligent":[74],"nodes":[75],"network.":[78],"global":[81],"communication,":[82],"power":[83],"conversion":[84],"management,":[86],"synchronization,":[87],"memory":[90],"capabilities,":[91],"redundancy":[92],"allocation,":[93],"test":[95],"Si-IF,":[98],"functional":[103],"dies.":[104]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}