{"id":"https://openalex.org/W2610740845","doi":"https://doi.org/10.1109/isqed.2017.7918352","title":"Systematic approximate logic optimization using don't care conditions","display_name":"Systematic approximate logic optimization using don't care conditions","publication_year":2017,"publication_date":"2017-03-01","ids":{"openalex":"https://openalex.org/W2610740845","doi":"https://doi.org/10.1109/isqed.2017.7918352","mag":"2610740845"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2017.7918352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2017.7918352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 18th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032477215","display_name":"Sahand Salamat","orcid":"https://orcid.org/0000-0002-3022-8212"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Sahand Salamat","raw_affiliation_strings":["College of Engineering, University of Tehran, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103008803","display_name":"Mehrnaz Ahmadi","orcid":"https://orcid.org/0009-0007-3195-9475"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mehrnaz Ahmadi","raw_affiliation_strings":["College of Engineering, University of Tehran, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069623023","display_name":"Bijan Alizadeh","orcid":"https://orcid.org/0000-0003-4436-4597"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]},{"id":"https://openalex.org/I4210146419","display_name":"Institute for Research in Fundamental Sciences","ror":"https://ror.org/04xreqs31","country_code":"IR","type":"facility","lineage":["https://openalex.org/I4210146419"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Bijan Alizadeh","raw_affiliation_strings":["College of Engineering, University of Tehran, Tehran, Iran","School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"College of Engineering, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran","institution_ids":["https://openalex.org/I4210146419"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5032477215"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":1.2901,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.81285329,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"419","last_page":"425"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7534503936767578},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.674542248249054},{"id":"https://openalex.org/keywords/approximation-error","display_name":"Approximation error","score":0.6634949445724487},{"id":"https://openalex.org/keywords/approximation-algorithm","display_name":"Approximation algorithm","score":0.6049075126647949},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5700989961624146},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5592039823532104},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46825891733169556},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45671477913856506},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4488725960254669},{"id":"https://openalex.org/keywords/approximation-theory","display_name":"Approximation theory","score":0.42807742953300476},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.38541263341903687},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33845946192741394},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21005219221115112},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09017786383628845},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08628684282302856}],"concepts":[{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7534503936767578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.674542248249054},{"id":"https://openalex.org/C122383733","wikidata":"https://www.wikidata.org/wiki/Q865920","display_name":"Approximation error","level":2,"score":0.6634949445724487},{"id":"https://openalex.org/C148764684","wikidata":"https://www.wikidata.org/wiki/Q621751","display_name":"Approximation algorithm","level":2,"score":0.6049075126647949},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5700989961624146},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5592039823532104},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46825891733169556},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45671477913856506},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4488725960254669},{"id":"https://openalex.org/C145242015","wikidata":"https://www.wikidata.org/wiki/Q774123","display_name":"Approximation theory","level":2,"score":0.42807742953300476},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.38541263341903687},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33845946192741394},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21005219221115112},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09017786383628845},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08628684282302856},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2017.7918352","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2017.7918352","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 18th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1565813530","https://openalex.org/W1988290377","https://openalex.org/W2053568314","https://openalex.org/W2082738287","https://openalex.org/W2097325076","https://openalex.org/W2105216798","https://openalex.org/W2125749871","https://openalex.org/W2153848924","https://openalex.org/W2164241781","https://openalex.org/W2214603015","https://openalex.org/W2287282306","https://openalex.org/W3145331805","https://openalex.org/W4231091214","https://openalex.org/W4247892942","https://openalex.org/W6647363498"],"related_works":["https://openalex.org/W2044115164","https://openalex.org/W2110817230","https://openalex.org/W4308701628","https://openalex.org/W1606488336","https://openalex.org/W2014137052","https://openalex.org/W2165420145","https://openalex.org/W2171221472","https://openalex.org/W1988569331","https://openalex.org/W189995875","https://openalex.org/W3091355678"],"abstract_inverted_index":{"Approximate":[0],"computing":[1],"has":[2],"emerged":[3],"as":[4],"a":[5,32,60],"new":[6],"design":[7],"paradigm":[8],"in":[9,20,45,82],"wide":[10],"variety":[11],"error":[12,43,46],"resilient":[13],"applications":[14,48],"to":[15,49,64,89],"decrease":[16],"the":[17,25,40,66,71,74,90],"hardware":[18],"cost":[19],"an":[21,51],"acceptable":[22],"deviation":[23],"from":[24],"nominal":[26],"output":[27],"values.":[28],"In":[29],"this":[30],"paper,":[31],"logic":[33],"approximation":[34,52,92],"technique":[35],"is":[36,62],"proposed":[37,63,75],"which":[38,69],"takes":[39],"advantage":[41],"of":[42,73],"budget":[44],"tolerant":[47],"achieve":[50],"circuit":[53],"with":[54],"smaller":[55],"area":[56,83],"and":[57,84],"latency.":[58],"Moreover,":[59],"heuristic":[61],"prune":[65],"search":[67],"space,":[68],"increases":[70],"scalability":[72],"technique.":[76],"The":[77],"results":[78],"show":[79],"38.3%":[80],"reduction":[81],"26.6\u00d7":[85],"speed":[86],"up":[87],"compared":[88],"state-of-the-art":[91],"techniques.":[93]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2018,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}