{"id":"https://openalex.org/W2396963594","doi":"https://doi.org/10.1109/isqed.2016.7479240","title":"Fully automated PLL compiler generating final GDS from specification","display_name":"Fully automated PLL compiler generating final GDS from specification","publication_year":2016,"publication_date":"2016-03-01","ids":{"openalex":"https://openalex.org/W2396963594","doi":"https://doi.org/10.1109/isqed.2016.7479240","mag":"2396963594"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2016.7479240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2016.7479240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071803491","display_name":"Toru Nakura","orcid":"https://orcid.org/0000-0001-5945-3918"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Toru Nakura","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), The University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), The University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VLSI Design and Education Center (VDEC), The University of Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), The University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5071803491"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.1874,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.5581552,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"437","last_page":"442"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8340576887130737},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7758410573005676},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.75228351354599},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.712764322757721},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4703669250011444},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.45848625898361206},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.43884342908859253},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32165682315826416},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2816579341888428},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24816015362739563},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.20846912264823914},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.14967572689056396},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11908158659934998}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8340576887130737},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7758410573005676},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.75228351354599},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.712764322757721},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4703669250011444},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.45848625898361206},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.43884342908859253},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32165682315826416},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2816579341888428},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24816015362739563},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.20846912264823914},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.14967572689056396},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11908158659934998},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2016.7479240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2016.7479240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1963906983","https://openalex.org/W2006427734","https://openalex.org/W2071216274","https://openalex.org/W2071523445","https://openalex.org/W2147533202","https://openalex.org/W6641183951"],"related_works":["https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W2103754166","https://openalex.org/W2043945969","https://openalex.org/W2082469970","https://openalex.org/W2058003010","https://openalex.org/W1994059163","https://openalex.org/W2117319580","https://openalex.org/W3113661469"],"abstract_inverted_index":{"This":[0],"paper":[1],"demonstrates":[2],"a":[3,22,130],"PLL":[4,16,24,48,67,81,125,160],"compiler":[5,49,82,126],"which":[6],"generates":[7,105,127],"GDS":[8],"data":[9],"from":[10],"performance":[11],"specification.":[12],"Pulse":[13],"Width":[14],"controlled":[15],"(PWPLL)":[17],"architecture":[18],"is":[19],"suitable":[20],"for":[21,46,114,129],"digital-flow":[23],"design,":[25],"and":[26,56,69,75,103,139,143,155],"there":[27],"are":[28,50],"8":[29,88],"design":[30,89,101,120],"parameters":[31,55],"in":[32],"PWPLL,":[33],"such":[34,122],"as":[35],"the":[36,41,57,62,70,80,87,95,100,106,115,124,145,148,152,158,163],"number":[37],"of":[38,40,73,86,135],"stages":[39],"ring":[42],"oscillator.":[43],"The":[44],"inputs":[45],"our":[47],"standard":[51],"cell":[52],"library,":[53],"SPICE":[54,92,169],"target":[58],"specification":[59],"file":[60],"defining":[61],"input":[63],"reference":[64],"frequency,":[65],"output":[66],"frequency":[68],"corner":[71,165],"conditions":[72,166],"TYP/BEST/WORST":[74],"other":[76],"PVT":[77],"conditions.":[78],"Then":[79],"calculates":[83],"rough":[84],"values":[85],"parameters,":[90,102],"runs":[91],"simulations,":[93],"analyzes":[94],"waveform":[96],"files":[97],"to":[98,150],"adjust":[99],"finally":[104],"gate-level":[107],"verilog":[108],"netlist":[109],"that":[110,123,157],"can":[111],"be":[112],"used":[113,117],"commonly":[116],"digital":[118,132],"circuit":[119],"flow,":[121],"scripts":[128,149],"commercial":[131],"tool":[133],"chain":[134],"P&R,":[136],"verification":[137],"(LVS/DRC)":[138],"RC":[140],"extraction":[141],"tools,":[142],"invokes":[144],"tools":[146],"with":[147],"generate":[151],"final":[153],"GDS,":[154],"confirms":[156],"compiled":[159],"locks":[161],"under":[162],"given":[164],"by":[167],"using":[168],"simulation.":[170]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
