{"id":"https://openalex.org/W2399814356","doi":"https://doi.org/10.1109/isqed.2016.7479219","title":"Nonlinear delay-table approach for full-chip NBTI degradation prediction","display_name":"Nonlinear delay-table approach for full-chip NBTI degradation prediction","publication_year":2016,"publication_date":"2016-03-01","ids":{"openalex":"https://openalex.org/W2399814356","doi":"https://doi.org/10.1109/isqed.2016.7479219","mag":"2399814356"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2016.7479219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2016.7479219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065421587","display_name":"Song Bian","orcid":"https://orcid.org/0000-0003-0467-6203"},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Song Bian","raw_affiliation_strings":["Dept. of Communications and Computer Engineering, Kyoto University"],"affiliations":[{"raw_affiliation_string":"Dept. of Communications and Computer Engineering, Kyoto University","institution_ids":["https://openalex.org/I22299242"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074380332","display_name":"Michihiro Shintani","orcid":"https://orcid.org/0000-0002-1163-096X"},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Michihiro Shintani","raw_affiliation_strings":["Dept. of Communications and Computer Engineering, Kyoto University"],"affiliations":[{"raw_affiliation_string":"Dept. of Communications and Computer Engineering, Kyoto University","institution_ids":["https://openalex.org/I22299242"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103082019","display_name":"Shumpei Morita","orcid":"https://orcid.org/0000-0002-5365-3537"},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shumpei Morita","raw_affiliation_strings":["Faculty of Engineering, Kyoto University, Kyoto, Japan"],"affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Kyoto University, Kyoto, Japan","institution_ids":["https://openalex.org/I22299242"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033255199","display_name":"Masayuki Hiromoto","orcid":null},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masayuki Hiromoto","raw_affiliation_strings":["Dept. of Communications and Computer Engineering, Kyoto University"],"affiliations":[{"raw_affiliation_string":"Dept. of Communications and Computer Engineering, Kyoto University","institution_ids":["https://openalex.org/I22299242"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017861176","display_name":"Takashi Sat\u014d","orcid":"https://orcid.org/0000-0002-1577-8259"},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takashi Sato","raw_affiliation_strings":["Dept. of Communications and Computer Engineering, Kyoto University"],"affiliations":[{"raw_affiliation_string":"Dept. of Communications and Computer Engineering, Kyoto University","institution_ids":["https://openalex.org/I22299242"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5065421587"],"corresponding_institution_ids":["https://openalex.org/I22299242"],"apc_list":null,"apc_paid":null,"fwci":1.43569814,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.85624046,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8526791930198669},{"id":"https://openalex.org/keywords/degradation","display_name":"Degradation (telecommunications)","score":0.7238044738769531},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.7058286070823669},{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.691611647605896},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6751673221588135},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5839025378227234},{"id":"https://openalex.org/keywords/circuit-reliability","display_name":"Circuit reliability","score":0.5408916473388672},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48683303594589233},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.4523438513278961},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4511248469352722},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44251111149787903},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4280737042427063},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4244341254234314},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4214571714401245},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.295646607875824},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2132459282875061},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19734248518943787},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19399327039718628},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1688043475151062},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16228145360946655},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1397569179534912},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1303180754184723},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.09606137871742249}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8526791930198669},{"id":"https://openalex.org/C2779679103","wikidata":"https://www.wikidata.org/wiki/Q5251805","display_name":"Degradation (telecommunications)","level":2,"score":0.7238044738769531},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.7058286070823669},{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.691611647605896},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6751673221588135},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5839025378227234},{"id":"https://openalex.org/C2778309119","wikidata":"https://www.wikidata.org/wiki/Q5121614","display_name":"Circuit reliability","level":4,"score":0.5408916473388672},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48683303594589233},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.4523438513278961},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4511248469352722},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44251111149787903},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4280737042427063},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4244341254234314},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4214571714401245},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.295646607875824},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2132459282875061},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19734248518943787},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19399327039718628},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1688043475151062},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16228145360946655},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1397569179534912},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1303180754184723},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.09606137871742249},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2016.7479219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2016.7479219","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1970620885","https://openalex.org/W2000301874","https://openalex.org/W2046094701","https://openalex.org/W2047663435","https://openalex.org/W2102729267","https://openalex.org/W2109042184","https://openalex.org/W2113996606","https://openalex.org/W2169033838","https://openalex.org/W2313603595","https://openalex.org/W3005347330","https://openalex.org/W4205623694","https://openalex.org/W4285719527","https://openalex.org/W6662038984","https://openalex.org/W6676279030","https://openalex.org/W6773842061"],"related_works":["https://openalex.org/W1970920853","https://openalex.org/W2099679924","https://openalex.org/W2738622559","https://openalex.org/W1977755957","https://openalex.org/W2115165828","https://openalex.org/W1982822282","https://openalex.org/W2076372184","https://openalex.org/W2471494153","https://openalex.org/W4233474994","https://openalex.org/W2156064231"],"abstract_inverted_index":{"As":[0],"technology":[1],"further":[2],"scales":[3],"semiconductor":[4],"devices,":[5],"aging-induced":[6,21,65],"device":[7,17],"degradation":[8,22,66,79],"has":[9],"become":[10],"one":[11],"of":[12,34,75,119],"the":[13,26,32,35,57,64,110,114,133,138,144],"major":[14],"threats":[15],"to":[16],"reliability.":[18],"Hence,":[19],"taking":[20],"into":[23],"account":[24],"during":[25],"design":[27,134],"phase":[28],"can":[29,122],"greatly":[30],"improve":[31],"reliability":[33],"manufactured":[36],"devices.":[37],"However,":[38],"considering":[39],"instance-dependent":[40],"Vth":[41],"degradations":[42],"for":[43,94],"extremely":[44],"large":[45],"circuits,":[46],"like":[47],"processors,":[48],"is":[49,97],"time-consuming.":[50],"In":[51],"this":[52],"research,":[53],"we":[54,153],"focus":[55],"on":[56],"negative":[58],"bias":[59],"temperature":[60],"instability":[61],"(NBTI)":[62],"as":[63,109,132],"mechanism,":[67],"and":[68,72,85,106],"propose":[69],"a":[70,127,149],"fast":[71],"efficient":[73],"way":[74],"estimating":[76],"NBTI-induced":[77],"delay":[78,91,140,146,160],"by":[80,136,148],"utilizing":[81],"static-timing":[82],"analysis":[83],"(STA)":[84],"simulation-based":[86],"lookup":[87],"table":[88,111],"(LUT).":[89],"Probability-based":[90],"model":[92],"(PBDM)":[93],"each":[95],"gate":[96],"characterized":[98],"in":[99],"advance,":[100],"having":[101],"input":[102],"slews,":[103],"output":[104],"capacitances":[105],"signal":[107],"probabilities":[108],"indices.":[112],"Using":[113],"PBDM":[115],"modeled,":[116],"path":[117],"delays":[118],"arbitrary":[120],"circuits":[121],"be":[123],"efficiently":[124],"estimated.":[125],"With":[126],"typical":[128],"five-stage":[129],"pipelined":[130],"processor":[131],"target,":[135],"comparing":[137],"calculated":[139,147],"from":[141],"LUT":[142],"with":[143],"reference":[145],"commercial":[150],"circuit":[151],"simulator,":[152],"achieved":[154],"4114":[155],"times":[156],"speedup":[157],"within":[158],"5.6%":[159],"error.":[161]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
