{"id":"https://openalex.org/W2404791559","doi":"https://doi.org/10.1109/isqed.2016.7479198","title":"An effective BIST architecture for power-gating mechanisms in low-power SRAMs","display_name":"An effective BIST architecture for power-gating mechanisms in low-power SRAMs","publication_year":2016,"publication_date":"2016-03-01","ids":{"openalex":"https://openalex.org/W2404791559","doi":"https://doi.org/10.1109/isqed.2016.7479198","mag":"2404791559"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2016.7479198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2016.7479198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074986688","display_name":"Alberto Bosio","orcid":"https://orcid.org/0000-0001-6116-7339"},"institutions":[{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Alberto Bosio","raw_affiliation_strings":["LIRMM, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Montpellier, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001777299","display_name":"Luigi Dilillo","orcid":"https://orcid.org/0000-0002-1295-2688"},"institutions":[{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Luigi Dilillo","raw_affiliation_strings":["LIRMM, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Montpellier, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005116115","display_name":"Patrick Girard","orcid":"https://orcid.org/0000-0003-0722-8772"},"institutions":[{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Patrick Girard","raw_affiliation_strings":["LIRMM, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Montpellier, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089236739","display_name":"A. Virazel","orcid":"https://orcid.org/0000-0001-7398-7107"},"institutions":[{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4412460525"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Arnaud Virazel","raw_affiliation_strings":["LIRMM, Montpellier, France"],"affiliations":[{"raw_affiliation_string":"LIRMM, Montpellier, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000960055","display_name":"Leonardo B. Zordan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Leonardo B. Zordan","raw_affiliation_strings":["Intel Mobile Communication, Sophia Antipolis, France"],"affiliations":[{"raw_affiliation_string":"Intel Mobile Communication, Sophia Antipolis, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5074986688"],"corresponding_institution_ids":["https://openalex.org/I4210101743"],"apc_list":null,"apc_paid":null,"fwci":0.3725,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.648572,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"185","last_page":"191"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8332017660140991},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7091367840766907},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5757673978805542},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5504093766212463},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.5340266227722168},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.5211896300315857},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48458540439605713},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4454197585582733},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.438515841960907},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4119688868522644},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4109543561935425},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.36275380849838257},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3621631860733032},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2632119059562683},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24903878569602966},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2279997169971466},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.19733339548110962},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1896277666091919}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8332017660140991},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7091367840766907},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5757673978805542},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5504093766212463},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.5340266227722168},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.5211896300315857},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48458540439605713},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4454197585582733},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.438515841960907},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4119688868522644},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4109543561935425},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.36275380849838257},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3621631860733032},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2632119059562683},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24903878569602966},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2279997169971466},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.19733339548110962},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1896277666091919},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isqed.2016.7479198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2016.7479198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 17th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:lirmm-01457424v1","is_oa":false,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-01457424","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.isqed.org/English/Archives/2016/","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W57117937","https://openalex.org/W974193658","https://openalex.org/W1744063783","https://openalex.org/W2009987317","https://openalex.org/W2141041201","https://openalex.org/W2143643276"],"related_works":["https://openalex.org/W3127845477","https://openalex.org/W2145376025","https://openalex.org/W2938543345","https://openalex.org/W2421981162","https://openalex.org/W1583123542","https://openalex.org/W2052583367","https://openalex.org/W2102121056","https://openalex.org/W2130965751","https://openalex.org/W4247326638","https://openalex.org/W2003272148"],"abstract_inverted_index":{"In":[0,43,66],"low-power":[1,51,81],"SRAMs,":[2,52],"power-gating":[3,78],"mechanisms":[4,24,58],"are":[5],"commonly":[6],"used":[7],"to":[8,45,104],"reduce":[9],"static":[10,47],"power":[11,48,56],"consumption.":[12],"When":[13],"the":[14,87,91,99,105],"SRAM":[15],"is":[16],"not":[17],"accessed":[18],"for":[19],"a":[20],"long":[21],"period,":[22],"such":[23],"allow":[25],"shutting-off":[26],"one":[27],"or":[28],"more":[29],"memory":[30],"blocks":[31],"(core-cell":[32],"array,":[33],"address":[34],"decoder,":[35],"I/O":[36],"logic,":[37],"etc),":[38],"thus":[39],"reducing":[40],"leakage":[41],"currents.":[42],"order":[44],"guarantee":[46],"reduction":[49],"in":[50,80],"reliable":[53],"operation":[54],"of":[55],"gating":[57],"must":[59],"be":[60],"ensured":[61],"by":[62],"adequate":[63],"test":[64,101],"techniques.":[65],"this":[67],"paper,":[68],"we":[69],"present":[70],"an":[71],"efficient":[72],"Built-In-Self-Test":[73],"architecture":[74],"targeting":[75],"defects":[76],"affecting":[77],"circuitry":[79],"SRAMs.":[82],"Experimental":[83],"results":[84],"show":[85],"that":[86],"proposed":[88],"solution":[89],"improves":[90],"defect":[92],"coverage":[93],"and":[94],"thus,":[95],"it":[96],"significantly":[97],"increases":[98],"overall":[100],"quality":[102],"compared":[103],"state-of-the-art.":[106]},"counts_by_year":[{"year":2017,"cited_by_count":2}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}