{"id":"https://openalex.org/W2029575849","doi":"https://doi.org/10.1109/isqed.2015.7085417","title":"A scan shifting method based on clock gating of multiple groups for low power scan testing","display_name":"A scan shifting method based on clock gating of multiple groups for low power scan testing","publication_year":2015,"publication_date":"2015-03-01","ids":{"openalex":"https://openalex.org/W2029575849","doi":"https://doi.org/10.1109/isqed.2015.7085417","mag":"2029575849"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2015.7085417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2015.7085417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036881913","display_name":"Sungyoul Seo","orcid":"https://orcid.org/0000-0001-9469-758X"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungyoul Seo","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","Department of Electrical and Electronic Engineering , Yonsei University , Seoul , Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering , Yonsei University , Seoul , Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100627843","display_name":"Yong Lee","orcid":"https://orcid.org/0000-0001-7843-8422"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yong Lee","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","Department of Electrical and Electronic Engineering , Yonsei University , Seoul , Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering , Yonsei University , Seoul , Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005942431","display_name":"Joo-Hwan Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Joohwan Lee","raw_affiliation_strings":["Samsung Electronics, Korea","[SAMSUNG Electronics, Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics, Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"[SAMSUNG Electronics, Korea]","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068528309","display_name":"Sungho Kang","orcid":"https://orcid.org/0000-0002-7093-2095"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungho Kang","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","Department of Electrical and Electronic Engineering , Yonsei University , Seoul , Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Department of Electrical and Electronic Engineering , Yonsei University , Seoul , Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.2944,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.92046632,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"162","last_page":"166"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.7533780336380005},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.694261372089386},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6663221120834351},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6356931924819946},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.576035737991333},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5587568283081055},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.500009298324585},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.472986102104187},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.460527241230011},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.45487698912620544},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44832295179367065},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4367064833641052},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4366443157196045},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.41358494758605957},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3644132614135742},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.347573459148407},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3247722387313843},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.27384018898010254},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23311525583267212},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2255115509033203},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.21498918533325195},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.15785002708435059},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.14992401003837585},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11095184087753296}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.7533780336380005},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.694261372089386},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6663221120834351},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6356931924819946},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.576035737991333},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5587568283081055},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.500009298324585},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.472986102104187},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.460527241230011},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.45487698912620544},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44832295179367065},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4367064833641052},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4366443157196045},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.41358494758605957},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3644132614135742},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.347573459148407},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3247722387313843},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.27384018898010254},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23311525583267212},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2255115509033203},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.21498918533325195},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.15785002708435059},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.14992401003837585},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11095184087753296},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2015.7085417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2015.7085417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Sixteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1978040115","https://openalex.org/W2057660425","https://openalex.org/W2059328769","https://openalex.org/W2096036637","https://openalex.org/W2103252557","https://openalex.org/W2104677752","https://openalex.org/W2105200922","https://openalex.org/W2112564358","https://openalex.org/W2114018023","https://openalex.org/W2118985907","https://openalex.org/W2119691242","https://openalex.org/W2123862221","https://openalex.org/W2133769728","https://openalex.org/W2136680550","https://openalex.org/W2144888713","https://openalex.org/W2152720440","https://openalex.org/W2160621850","https://openalex.org/W2170530584","https://openalex.org/W3143633214","https://openalex.org/W6675491065","https://openalex.org/W6680497249"],"related_works":["https://openalex.org/W2752479413","https://openalex.org/W2553035740","https://openalex.org/W2111928029","https://openalex.org/W2134712318","https://openalex.org/W1501621551","https://openalex.org/W29481652","https://openalex.org/W2117171289","https://openalex.org/W2189059878","https://openalex.org/W2110102663","https://openalex.org/W2166402441"],"abstract_inverted_index":{"From":[0],"the":[1,22,38,64,78,83,91,114,129],"advent":[2],"of":[3,14,21,29,56,63,77,96,123,128],"very":[4],"large":[5,27],"scale":[6],"integration":[7],"(VLSI)":[8],"design,":[9],"a":[10,15,47,126],"larger":[11],"power":[12,117],"consumption":[13],"scan-based":[16],"testing":[17],"has":[18],"been":[19],"one":[20],"most":[23],"serious":[24],"problems.":[25],"The":[26],"number":[28],"scan":[30,39,49,79,115],"cells":[31],"lead":[32],"to":[33,135],"excessive":[34],"switching":[35],"activities":[36],"during":[37],"shifting":[40,50,75,111,116],"operations.":[41],"In":[42,81,121],"this":[43,110],"paper,":[44],"we":[45],"present":[46],"new":[48],"method":[51,69,93,112],"based":[52],"on":[53,101],"clock":[54],"gating":[55],"multiple":[57],"groups":[58],"by":[59,74],"reducing":[60],"toggle":[61],"rate":[62],"internal":[65],"combinational":[66],"logic.":[67],"This":[68],"prevents":[70],"cumulative":[71],"transitions":[72],"caused":[73],"operations":[76],"cells.":[80],"addition,":[82],"existing":[84],"compression":[85],"schemes":[86],"can":[87],"be":[88,136],"compatible":[89],"with":[90],"proposed":[92],"without":[94],"modification":[95],"decompression":[97],"architecture.":[98],"Experimental":[99],"results":[100],"ITC'99":[102],"benchmark":[103],"circuits":[104,107],"and":[105],"industrial":[106],"show":[108],"that":[109],"reduces":[113],"in":[118],"all":[119],"cases.":[120],"spite":[122],"outperformed":[124],"power,":[125],"burden":[127],"extra":[130],"logic":[131],"is":[132],"not":[133],"necessary":[134],"contemplated.":[137]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}