{"id":"https://openalex.org/W2045570302","doi":"https://doi.org/10.1109/isqed.2014.6783399","title":"On pattern generation for maximizing IR drop","display_name":"On pattern generation for maximizing IR drop","publication_year":2014,"publication_date":"2014-03-01","ids":{"openalex":"https://openalex.org/W2045570302","doi":"https://doi.org/10.1109/isqed.2014.6783399","mag":"2045570302"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2014.6783399","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783399","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101651494","display_name":"Arunkumar Vijayakumar","orcid":"https://orcid.org/0000-0002-8843-9004"},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arunkumar Vijayakumar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA","Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA","institution_ids":["https://openalex.org/I24603500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA","institution_ids":["https://openalex.org/I24603500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080028094","display_name":"Vinay C. Patil","orcid":"https://orcid.org/0000-0001-9076-2727"},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vinay C Patil","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA","Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA","institution_ids":["https://openalex.org/I24603500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA","institution_ids":["https://openalex.org/I24603500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010763285","display_name":"Girish Paladugu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210137977","display_name":"Advanced Micro Devices (United States)","ror":"https://ror.org/04kd6c783","country_code":"US","type":"company","lineage":["https://openalex.org/I4210137977"]},{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA","US"],"is_corresponding":false,"raw_author_name":"Girish Paladugu","raw_affiliation_strings":["Advanced Micro Devices, Boxborough, USA","[Advanced Micro Devices, Boxborough, MA, USA]"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Boxborough, USA","institution_ids":["https://openalex.org/I4210137977"]},{"raw_affiliation_string":"[Advanced Micro Devices, Boxborough, MA, USA]","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054064879","display_name":"Sandip Kundu","orcid":"https://orcid.org/0000-0001-8221-3824"},"institutions":[{"id":"https://openalex.org/I24603500","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521","country_code":"US","type":"education","lineage":["https://openalex.org/I24603500"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandip Kundu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA","Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA","institution_ids":["https://openalex.org/I24603500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA","institution_ids":["https://openalex.org/I24603500"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101651494"],"corresponding_institution_ids":["https://openalex.org/I24603500"],"apc_list":null,"apc_paid":null,"fwci":1.2259,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.79279759,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":"163","issue":null,"first_page":"731","last_page":"737"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.696473240852356},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5783689022064209},{"id":"https://openalex.org/keywords/voltage-drop","display_name":"Voltage drop","score":0.5699323415756226},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4965434670448303},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48628294467926025},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.45890113711357117},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43546539545059204},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4108089208602905},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40865007042884827},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3572048246860504},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3553900718688965},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.34742945432662964},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2740507423877716},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2546619176864624},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24847453832626343}],"concepts":[{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.696473240852356},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5783689022064209},{"id":"https://openalex.org/C82178898","wikidata":"https://www.wikidata.org/wiki/Q166839","display_name":"Voltage drop","level":3,"score":0.5699323415756226},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4965434670448303},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48628294467926025},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.45890113711357117},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43546539545059204},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4108089208602905},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40865007042884827},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3572048246860504},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3553900718688965},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.34742945432662964},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2740507423877716},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2546619176864624},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24847453832626343}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2014.6783399","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783399","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2018386086","https://openalex.org/W2035863366","https://openalex.org/W2091127607","https://openalex.org/W2112173236","https://openalex.org/W2115762432","https://openalex.org/W2124089733","https://openalex.org/W2138858358","https://openalex.org/W2140000007","https://openalex.org/W2155487205","https://openalex.org/W2167501436","https://openalex.org/W2168853928","https://openalex.org/W3141794462","https://openalex.org/W3150017234","https://openalex.org/W6677341922","https://openalex.org/W6682885994","https://openalex.org/W6684835117"],"related_works":["https://openalex.org/W2108172432","https://openalex.org/W2119232911","https://openalex.org/W2143381869","https://openalex.org/W4245545105","https://openalex.org/W121910558","https://openalex.org/W1576517490","https://openalex.org/W2074526596","https://openalex.org/W4255681223","https://openalex.org/W4242010157","https://openalex.org/W1987230547"],"abstract_inverted_index":{"Increase":[0],"in":[1,6,10,23,28,33,197,247],"power":[2,12,44,119,140],"density":[3],"and":[4,90,182,187,221,245,256],"decrease":[5],"supply":[7,13,24,34,45,120,141],"voltage":[8],"results":[9,27],"greater":[11],"current.":[14],"With":[15],"scaling,":[16],"line":[17],"resistance":[18],"increases.":[19],"Together":[20],"with":[21,252],"increase":[22],"current,":[25],"this":[26,97,144,167],"ever":[29],"larger":[30,234],"IR":[31,36,49,68,115,132],"drop":[32,37,50,69,116,133,264],"voltage.":[35],"analysis":[38,102,145],"is":[39,51,72,230],"an":[40,53,198,269],"important":[41,54],"element":[42],"of":[43,56,87,113,117,153,166,172,184,218,225,278],"network":[46,121],"design.":[47],"Maximizing":[48],"also":[52],"component":[55],"manufacturing":[57],"testing.":[58],"As":[59],"a":[60,118,126,135,151],"CMOS":[61],"gate":[62],"primarily":[63],"draws":[64],"current":[65],"during":[66],"switching,":[67],"maximization":[70],"problem":[71,103,112,129],"akin":[73],"to":[74,109,130,195,233,241],"finding":[75],"input":[76],"pattern":[77,127,176,206,254],"pair":[78],"that":[79,212,251],"maximizes":[80],"circuit":[81],"switching":[82],"taking":[83],"the":[84,88,110,139,161,179,185,190,205,215,222,228],"drive":[85],"strengths":[86,183],"gates":[89,186,194],"their":[91],"spatial":[92,180],"distribution":[93,159],"into":[94],"consideration.":[95],"In":[96],"paper,":[98],"we":[99,259],"examine":[100],"IR-drop":[101],"for":[104,175,203],"combinational":[105,219],"circuits.":[106,235],"The":[107,163,236],"solution":[108],"general":[111],"maximizing":[114],"can":[122,146],"be":[123,148],"reformulated":[124],"as":[125,143],"generation":[128,177,207,255],"maximize":[131],"at":[134],"specific":[136],"point":[137],"on":[138,150,160,268],"network,":[142],"then":[147],"applied":[149,232,240],"collection":[152],"target":[154],"points":[155],"determined":[156],"by":[157,213,275],"load":[158],"grid.":[162],"main":[164],"contributions":[165],"paper":[168],"are":[169],"(i)":[170],"formulation":[171,224],"objective":[173,226],"function":[174],"using":[178],"location":[181],"(ii)":[188],"expressing":[189],"Boolean":[191],"relationships":[192],"between":[193],"use":[196],"Integer":[199],"Linear":[200],"Programming":[201],"solver":[202],"solving":[204],"problem.":[208],"We":[209],"further":[210],"show":[211,250],"exploiting":[214],"conic":[216],"structure":[217],"circuits":[220,244],"proposed":[223,237],"function,":[227],"technique":[229,238],"easily":[231],"was":[239],"ISCAS-85":[242],"benchmark":[243],"validated":[246],"simulation.":[248],"Results":[249],"targeted":[253],"deterministic":[257],"approach,":[258],"achieve":[260],"~25":[261],"%":[262],"moreIR":[263],"over":[265],"random":[266],"patterns":[267],"average,":[270],"while":[271],"average":[272],"run-time":[273],"improves":[274],"four":[276],"orders":[277],"magnitude.":[279]},"counts_by_year":[{"year":2016,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
