{"id":"https://openalex.org/W2017495018","doi":"https://doi.org/10.1109/isqed.2014.6783382","title":"Specification and formal verification of power gating in processors","display_name":"Specification and formal verification of power gating in processors","publication_year":2014,"publication_date":"2014-03-01","ids":{"openalex":"https://openalex.org/W2017495018","doi":"https://doi.org/10.1109/isqed.2014.6783382","mag":"2017495018"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2014.6783382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053471252","display_name":"Amir Masoud Gharehbaghi","orcid":"https://orcid.org/0000-0002-0451-221X"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]},{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Amir Masoud Gharehbaghi","raw_affiliation_strings":["Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan","[Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]},{"raw_affiliation_string":"[Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan]","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]},{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan","[VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]},{"raw_affiliation_string":"[VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan]","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5053471252"],"corresponding_institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":1.0682,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.77019128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1427","issue":null,"first_page":"604","last_page":"610"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8183784484863281},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.7323298454284668},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.7316402196884155},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.6259716749191284},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.605023980140686},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.5056436061859131},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.5056352615356445},{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.4731627106666565},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.4634762704372406},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.4396919012069702},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.43414241075515747},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.43110066652297974},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.42004215717315674},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4121451675891876},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38186115026474},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3791406452655792},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.353974312543869},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.16006115078926086},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.08000266551971436},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07701155543327332},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.07667902112007141}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8183784484863281},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.7323298454284668},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.7316402196884155},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.6259716749191284},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.605023980140686},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.5056436061859131},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.5056352615356445},{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.4731627106666565},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.4634762704372406},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.4396919012069702},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.43414241075515747},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.43110066652297974},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.42004215717315674},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4121451675891876},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38186115026474},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3791406452655792},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.353974312543869},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.16006115078926086},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.08000266551971436},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07701155543327332},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.07667902112007141},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2014.6783382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1553731663","https://openalex.org/W1592502301","https://openalex.org/W1741528175","https://openalex.org/W1751589996","https://openalex.org/W1998492944","https://openalex.org/W2026096005","https://openalex.org/W2110011370","https://openalex.org/W2118154221","https://openalex.org/W2151494804","https://openalex.org/W3146616442","https://openalex.org/W6635458761","https://openalex.org/W6637675132","https://openalex.org/W6727681760"],"related_works":["https://openalex.org/W2106507440","https://openalex.org/W3023586562","https://openalex.org/W2162615969","https://openalex.org/W1928822090","https://openalex.org/W2800324237","https://openalex.org/W3120172095","https://openalex.org/W3082696694","https://openalex.org/W2105593427","https://openalex.org/W1972950378","https://openalex.org/W2167855737"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,25,32,62],"method":[4,44,68,78],"for":[5,45],"specification":[6],"as":[7,9,27],"well":[8],"efficient":[10,43],"formal":[11],"verification":[12,71],"of":[13,17,24,48],"power":[14,37],"gating":[15,38],"feature":[16],"processors.":[18],"Given":[19],"an":[20,42],"instruction-set":[21],"architecture":[22],"model":[23,35],"processor,":[26],"the":[28,49,70,75],"golden":[29],"model,":[30],"and":[31,55],"detailed":[33],"processor":[34,64],"with":[36],"feature,":[39],"we":[40],"propose":[41],"equivalence":[46],"checking":[47,77],"two":[50],"models":[51],"using":[52],"symbolic":[53],"simulation":[54],"property":[56],"checking.":[57],"Our":[58],"experimental":[59],"results":[60],"on":[61],"MIPS":[63],"shows":[65],"that":[66],"our":[67],"reduces":[69],"time":[72],"compared":[73],"to":[74],"correspondence":[76],"at":[79],"least":[80],"by":[81],"3.4x.":[82]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}