{"id":"https://openalex.org/W2069309106","doi":"https://doi.org/10.1109/isqed.2014.6783379","title":"Assertion-based verification for system-level designs","display_name":"Assertion-based verification for system-level designs","publication_year":2014,"publication_date":"2014-03-01","ids":{"openalex":"https://openalex.org/W2069309106","doi":"https://doi.org/10.1109/isqed.2014.6783379","mag":"2069309106"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2014.6783379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027847347","display_name":"Hassan Sohofi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Hassan Sohofi","raw_affiliation_strings":["University of Tehran, School of Electrical and Computer Engineering, Tehran, Iran","[Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"University of Tehran, School of Electrical and Computer Engineering, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007933406","display_name":"Zainalabedin Navabi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Zainalabedin Navabi","raw_affiliation_strings":["University of Tehran, School of Electrical and Computer Engineering, Tehran, Iran","[Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]"],"affiliations":[{"raw_affiliation_string":"University of Tehran, School of Electrical and Computer Engineering, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"[Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran]","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5027847347"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":2.4518,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.8934717,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"582","last_page":"588"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8228997588157654},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8002759218215942},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.7588268518447876},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.6552138328552246},{"id":"https://openalex.org/keywords/assertion","display_name":"Assertion","score":0.6526159644126892},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.636446475982666},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.5858253836631775},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5210422873497009},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5030369162559509},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.4431854784488678},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4416748881340027},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.4205586910247803},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41571491956710815},{"id":"https://openalex.org/keywords/runtime-verification","display_name":"Runtime verification","score":0.41366565227508545},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.373294472694397},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.19069606065750122},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1757606863975525},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.1564335823059082},{"id":"https://openalex.org/keywords/software-construction","display_name":"Software construction","score":0.0750943124294281}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8228997588157654},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8002759218215942},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.7588268518447876},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.6552138328552246},{"id":"https://openalex.org/C40422974","wikidata":"https://www.wikidata.org/wiki/Q741248","display_name":"Assertion","level":2,"score":0.6526159644126892},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.636446475982666},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.5858253836631775},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5210422873497009},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5030369162559509},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.4431854784488678},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4416748881340027},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.4205586910247803},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41571491956710815},{"id":"https://openalex.org/C202973057","wikidata":"https://www.wikidata.org/wiki/Q7380130","display_name":"Runtime verification","level":3,"score":0.41366565227508545},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.373294472694397},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.19069606065750122},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1757606863975525},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.1564335823059082},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0750943124294281},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2014.6783379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1536590324","https://openalex.org/W1987222066","https://openalex.org/W1995597180","https://openalex.org/W2008339312","https://openalex.org/W2021625097","https://openalex.org/W2023777102","https://openalex.org/W2024158551","https://openalex.org/W2048677734","https://openalex.org/W2069603759","https://openalex.org/W2110676418","https://openalex.org/W2143062031","https://openalex.org/W2169490784","https://openalex.org/W2171573750","https://openalex.org/W2399260475","https://openalex.org/W3149600922","https://openalex.org/W6632200037","https://openalex.org/W6667966725"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2392047570","https://openalex.org/W2035244079","https://openalex.org/W2535719568","https://openalex.org/W2165346564","https://openalex.org/W1985271980","https://openalex.org/W2135756607","https://openalex.org/W2138343703","https://openalex.org/W4255789569","https://openalex.org/W2004066214"],"abstract_inverted_index":{"As":[0],"design":[1,62],"abstraction":[2],"has":[3],"now":[4],"got":[5],"to":[6,25],"its":[7],"next":[8],"upper":[9],"level":[10,70,104],"that":[11,28],"is":[12,23],"System":[13,32],"Level,":[14],"one":[15],"of":[16,109],"the":[17,107],"main":[18],"challenges":[19],"in":[20,78,85,106],"this":[21,35,73],"area":[22],"how":[24],"verify":[26],"designs":[27,46,75,99],"are":[29,38,57,76,83,91,100],"modeled":[30,77],"at":[31],"Level.":[33],"In":[34,72],"paper,":[36],"we":[37],"presenting":[39],"an":[40],"environment":[41,50],"for":[42,60,68],"functionally":[43],"verifying":[44],"system-level":[45],"using":[47,94],"assertions.":[48],"This":[49],"adapts":[51],"existing":[52],"EDA":[53],"simulation":[54],"tools,":[55],"which":[56],"mainly":[58],"used":[59],"RTL":[61],"and":[63,65,81,88,98],"verification,":[64],"utilizes":[66],"them":[67],"system":[69,103],"verification.":[71],"environment,":[74],"SystemC-TLM":[79],"2.0,":[80],"assertions":[82,105],"written":[84],"SystemVerilog.":[86],"Design":[87],"verification":[89],"parts":[90],"connected":[92],"together":[93],"SystemVerilog":[95],"DPI":[96],"mechanism,":[97],"verified":[101],"against":[102],"course":[108],"simulation.":[110]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}