{"id":"https://openalex.org/W1996492652","doi":"https://doi.org/10.1109/isqed.2014.6783331","title":"Measuring SET pulsewidths in logic gates using digital infrastructure","display_name":"Measuring SET pulsewidths in logic gates using digital infrastructure","publication_year":2014,"publication_date":"2014-03-01","ids":{"openalex":"https://openalex.org/W1996492652","doi":"https://doi.org/10.1109/isqed.2014.6783331","mag":"1996492652"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2014.6783331","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783331","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072775176","display_name":"Varadan Savulimedu Veeravalli","orcid":null},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Varadan Savulimedu Veeravalli","raw_affiliation_strings":["Department of Computer Engineering, Vienna University of Technology, Austria","Department of Computer Engineering, Vienna University of Technology, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Vienna University of Technology, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Department of Computer Engineering, Vienna University of Technology, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006749662","display_name":"Andreas Steininger","orcid":"https://orcid.org/0000-0002-3847-1647"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Andreas Steininger","raw_affiliation_strings":["Department of Computer Engineering, Vienna University of Technology, Austria","Department of Computer Engineering, Vienna University of Technology, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Vienna University of Technology, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Department of Computer Engineering, Vienna University of Technology, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006249454","display_name":"Ulrich Schmid","orcid":"https://orcid.org/0000-0001-9831-8583"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Ulrich Schmid","raw_affiliation_strings":["Department of Computer Engineering, Vienna University of Technology, Austria","Department of Computer Engineering, Vienna University of Technology, Vienna, Austria"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Vienna University of Technology, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Department of Computer Engineering, Vienna University of Technology, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5072775176"],"corresponding_institution_ids":["https://openalex.org/I145847075"],"apc_list":null,"apc_paid":null,"fwci":1.10988521,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.82143183,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"56","issue":null,"first_page":"236","last_page":"242"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6805459260940552},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6588326096534729},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.627444863319397},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6121803522109985},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6015251874923706},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5787946581840515},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.4884999990463257},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4877787232398987},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45632413029670715},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.41379982233047485},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2830336093902588},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21925652027130127},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13873982429504395},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09159991145133972}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6805459260940552},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6588326096534729},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.627444863319397},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6121803522109985},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6015251874923706},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5787946581840515},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.4884999990463257},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4877787232398987},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45632413029670715},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.41379982233047485},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2830336093902588},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21925652027130127},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13873982429504395},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09159991145133972},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2014.6783331","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783331","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1991458291","https://openalex.org/W1995560524","https://openalex.org/W2013415613","https://openalex.org/W2025761671","https://openalex.org/W2099569658","https://openalex.org/W2112103432","https://openalex.org/W2115516668","https://openalex.org/W2130199450","https://openalex.org/W2135410147","https://openalex.org/W2148121112","https://openalex.org/W2156322056","https://openalex.org/W2167839483","https://openalex.org/W3143589963","https://openalex.org/W3149410719","https://openalex.org/W4233171134"],"related_works":["https://openalex.org/W2170979950","https://openalex.org/W2039299085","https://openalex.org/W2991739378","https://openalex.org/W1980349267","https://openalex.org/W2098419840","https://openalex.org/W2140610743","https://openalex.org/W2116326546","https://openalex.org/W2097637358","https://openalex.org/W2151104031","https://openalex.org/W2765435638"],"abstract_inverted_index":{"We":[0,86],"present":[1],"a":[2,14,27,35,55,73],"purely":[3],"digital":[4],"infrastructure":[5],"for":[6,18,90],"measuring":[7],"SET":[8,24],"pulsewidths":[9],"in":[10,82],"logic":[11],"gates.":[12],"Such":[13],"facility":[15],"is":[16,77],"crucial":[17],"experimentally":[19],"studying":[20],"radiation":[21,65,81,93],"sensitivity":[22],"and":[23,52],"propagation":[25],"of":[26,42,61,101],"circuit.":[28],"Our":[29],"digital-only":[30],"implementation":[31],"facilitates":[32],"measurement":[33],"within":[34],"standard-cell":[36],"CMOS":[37],"chip,":[38],"without":[39],"the":[40,59,105],"need":[41],"any":[43],"analog":[44,97],"or":[45],"customized":[46],"circuitry":[47],"on-chip.":[48],"Besides":[49],"high":[50],"resolution":[51],"area":[53],"efficiency,":[54],"fundamental":[56],"requirement":[57],"guiding":[58],"development":[60],"our":[62,88],"solution":[63],"was":[64],"tolerance,":[66],"as":[67],"it":[68],"shall":[69],"be":[70],"employed":[71],"on":[72],"test":[74],"chip":[75],"that":[76],"fully":[78],"exposed":[79],"to":[80],"an":[83],"experimental":[84],"study.":[85],"validate":[87],"architecture,":[89],"various":[91],"primary":[92],"target":[94],"circuits,":[95],"by":[96],"simulation,":[98],"injecting":[99],"SETs":[100],"varying":[102],"strength":[103],"using":[104],"standard":[106],"double-exponential":[107],"current":[108],"model.":[109]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
