{"id":"https://openalex.org/W1977640839","doi":"https://doi.org/10.1109/isqed.2014.6783312","title":"An analytical approach to system-level variation analysis and optimization for multi-core processor","display_name":"An analytical approach to system-level variation analysis and optimization for multi-core processor","publication_year":2014,"publication_date":"2014-03-01","ids":{"openalex":"https://openalex.org/W1977640839","doi":"https://doi.org/10.1109/isqed.2014.6783312","mag":"1977640839"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2014.6783312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064738995","display_name":"Chenyun Pan","orcid":"https://orcid.org/0000-0001-9161-1728"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chenyun Pan","raw_affiliation_strings":["School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, USA","Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009591041","display_name":"Saibal Mukhopadhyay","orcid":"https://orcid.org/0000-0002-8894-3390"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saibal Mukhopadhyay","raw_affiliation_strings":["School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, USA","Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080526846","display_name":"Azad Naeemi","orcid":"https://orcid.org/0000-0003-4774-9046"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Azad Naeemi","raw_affiliation_strings":["School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, USA","Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5064738995"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56533332,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"99","last_page":"106"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7506066560745239},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.7449246644973755},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7231369018554688},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.62452632188797},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5319360494613647},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5277503132820129},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4722523093223572},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4464718699455261},{"id":"https://openalex.org/keywords/single-core","display_name":"Single-core","score":0.4359997808933258},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.43053242564201355},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3316744267940521}],"concepts":[{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7506066560745239},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7449246644973755},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7231369018554688},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.62452632188797},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5319360494613647},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5277503132820129},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4722523093223572},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4464718699455261},{"id":"https://openalex.org/C2780365336","wikidata":"https://www.wikidata.org/wiki/Q25047934","display_name":"Single-core","level":2,"score":0.4359997808933258},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.43053242564201355},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3316744267940521},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2014.6783312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2014.6783312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fifteenth International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1967709031","https://openalex.org/W2007156258","https://openalex.org/W2033443176","https://openalex.org/W2035720033","https://openalex.org/W2041684917","https://openalex.org/W2100227344","https://openalex.org/W2101554015","https://openalex.org/W2106450191","https://openalex.org/W2125669810","https://openalex.org/W2128418739","https://openalex.org/W2130494464","https://openalex.org/W2131862714","https://openalex.org/W2134565313","https://openalex.org/W2142726556","https://openalex.org/W2150283124","https://openalex.org/W2150526221","https://openalex.org/W2166703452","https://openalex.org/W3150134984","https://openalex.org/W3152285429","https://openalex.org/W6674970081","https://openalex.org/W6681499266"],"related_works":["https://openalex.org/W2142016460","https://openalex.org/W2151223307","https://openalex.org/W3041000698","https://openalex.org/W2406856881","https://openalex.org/W2085485158","https://openalex.org/W2276000909","https://openalex.org/W1964594690","https://openalex.org/W2049334739","https://openalex.org/W2543559046","https://openalex.org/W2022939529"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,27,45,60,78,94,118],"variation-aware":[4],"system-level":[5,33,69],"design":[6,24,55,63],"methodology":[7],"is":[8,49,107],"presented":[9],"to":[10,103,109],"analyze":[11],"the":[12,22,41,73,82,112],"throughput":[13,42,116],"distribution":[14,43],"under":[15],"power,":[16],"area":[17],"and":[18,35,68,85,91,114],"yield":[19,113],"constraints":[20],"at":[21],"early":[23],"stage":[25],"of":[26,44,75,117],"multi-core":[28,79,119],"processor.":[29,120],"Based":[30],"on":[31,77],"compact":[32],"models":[34],"circuit-level":[36],"Monte":[37],"Carlo":[38],"HSPICE":[39],"simulations,":[40],"single":[46],"core":[47,84],"processor":[48],"obtained":[50],"from":[51],"an":[52],"efficient":[53],"top-down":[54],"approach":[56],"that":[57,99],"enables":[58],"exploring":[59],"large":[61],"multi-parameter":[62],"space":[64],"spanning":[65],"device-,":[66],"circuit-,":[67],"parameters.":[70],"To":[71],"reduce":[72],"impact":[74],"variations":[76],"processor,":[80],"disabling":[81],"slowest":[83],"per-core":[86],"clocking":[87],"techniques":[88],"are":[89],"implemented":[90],"evaluated.":[92],"Finally,":[93],"novel":[95],"power":[96,102],"reallocating":[97],"technique":[98],"assigns":[100],"more":[101,104],"power-efficient":[105],"cores":[106],"proposed":[108],"further":[110],"improve":[111],"aggregate":[115]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
