{"id":"https://openalex.org/W2097434024","doi":"https://doi.org/10.1109/isqed.2013.6523676","title":"On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors","display_name":"On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors","publication_year":2013,"publication_date":"2013-03-01","ids":{"openalex":"https://openalex.org/W2097434024","doi":"https://doi.org/10.1109/isqed.2013.6523676","mag":"2097434024"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2013.6523676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2013.6523676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021728589","display_name":"Yiqiang Ding","orcid":null},"institutions":[{"id":"https://openalex.org/I184840846","display_name":"Virginia Commonwealth University","ror":"https://ror.org/02nkdxk79","country_code":"US","type":"education","lineage":["https://openalex.org/I184840846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yiqiang Ding","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, Va, USA","[Dept. of Electr. & Comput. Eng., Virginia Commonwealth Univ., Richmond, VA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, Va, USA","institution_ids":["https://openalex.org/I184840846"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Virginia Commonwealth Univ., Richmond, VA, USA]","institution_ids":["https://openalex.org/I184840846"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101767467","display_name":"Wei Zhang","orcid":"https://orcid.org/0009-0000-2717-5212"},"institutions":[{"id":"https://openalex.org/I184840846","display_name":"Virginia Commonwealth University","ror":"https://ror.org/02nkdxk79","country_code":"US","type":"education","lineage":["https://openalex.org/I184840846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, Va, USA","[Dept. of Electr. & Comput. Eng., Virginia Commonwealth Univ., Richmond, VA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, Va, USA","institution_ids":["https://openalex.org/I184840846"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Virginia Commonwealth Univ., Richmond, VA, USA]","institution_ids":["https://openalex.org/I184840846"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I184840846"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1744373,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"37 60","issue":null,"first_page":"627","last_page":"634"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9807999730110168,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9797999858856201,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8539137244224548},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.7949560284614563},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7426931858062744},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6882292628288269},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6506853699684143},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6190031170845032},{"id":"https://openalex.org/keywords/gang-scheduling","display_name":"Gang scheduling","score":0.41674450039863586},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4072279930114746},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.3393726944923401},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.2924230098724365},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.24323686957359314},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2157987654209137}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8539137244224548},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.7949560284614563},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7426931858062744},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6882292628288269},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6506853699684143},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6190031170845032},{"id":"https://openalex.org/C201515029","wikidata":"https://www.wikidata.org/wiki/Q5520966","display_name":"Gang scheduling","level":5,"score":0.41674450039863586},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4072279930114746},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.3393726944923401},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.2924230098724365},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.24323686957359314},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2157987654209137},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2013.6523676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2013.6523676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1805570991","https://openalex.org/W1943109230","https://openalex.org/W1980996541","https://openalex.org/W2054998117","https://openalex.org/W2069733180","https://openalex.org/W2076285066","https://openalex.org/W2101300711","https://openalex.org/W2109488193","https://openalex.org/W2119959854","https://openalex.org/W2122154156","https://openalex.org/W2133420723","https://openalex.org/W2134202349","https://openalex.org/W2137302811","https://openalex.org/W2138952175","https://openalex.org/W2162222856","https://openalex.org/W2171278566","https://openalex.org/W2171518785","https://openalex.org/W2397616328","https://openalex.org/W4285719527","https://openalex.org/W6679323028","https://openalex.org/W6712813235"],"related_works":["https://openalex.org/W2033778626","https://openalex.org/W2187110187","https://openalex.org/W2026780467","https://openalex.org/W2018697868","https://openalex.org/W2002371119","https://openalex.org/W2152099439","https://openalex.org/W2128523353","https://openalex.org/W4390492895","https://openalex.org/W2886225742","https://openalex.org/W2276754229"],"abstract_inverted_index":{"In":[0,51],"a":[1,48,78],"multicore":[2,62,121],"platform,":[3],"the":[4,11,27,30,66,87,101,106,109,119],"inter-thread":[5,68,89],"cache":[6,32,92],"interferences":[7,33,69,93],"can":[8,104],"significantly":[9],"affect":[10],"worst-case":[12,31,67,88],"execution":[13],"time":[14],"(WCET)":[15],"of":[16,108],"each":[17],"real-time":[18,58],"task,":[19],"which":[20],"is":[21],"crucial":[22],"for":[23],"schedulability":[24],"analysis.":[25],"At":[26],"same":[28],"time,":[29],"are":[34,39],"dependent":[35],"on":[36,43,61,70,115],"how":[37],"tasks":[38],"scheduled":[40],"to":[41,81,118],"run":[42],"different":[44],"cores,":[45],"thus":[46],"creating":[47],"circular":[49],"dependence.":[50],"this":[52],"paper,":[53],"we":[54],"present":[55],"an":[56],"offline":[57],"scheduling":[59,75,122],"approach":[60,76,103],"processors":[63],"by":[64,112],"considering":[65],"shared":[71,90],"L2":[72,91],"caches.":[73],"Our":[74],"uses":[77],"greedy":[79],"heuristic":[80],"generate":[82],"safe":[83],"schedules":[84],"while":[85],"minimizing":[86],"and":[94],"WCET.":[95],"The":[96],"experimental":[97],"results":[98],"demonstrate":[99],"that":[100],"proposed":[102],"reduce":[105],"utilization":[107],"resulting":[110],"schedule":[111],"about":[113],"12%":[114],"average":[116],"compared":[117],"cyclic":[120],"approaches":[123],"in":[124],"our":[125],"theoretical":[126],"model.":[127]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}