{"id":"https://openalex.org/W2134239612","doi":"https://doi.org/10.1109/isqed.2013.6523657","title":"Relocatable and resizable SRAM synthesis for via configurable structured ASIC","display_name":"Relocatable and resizable SRAM synthesis for via configurable structured ASIC","publication_year":2013,"publication_date":"2013-03-01","ids":{"openalex":"https://openalex.org/W2134239612","doi":"https://doi.org/10.1109/isqed.2013.6523657","mag":"2134239612"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2013.6523657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2013.6523657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069771268","display_name":"Hsin-Hung Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I99908691","display_name":"Yuan Ze University","ror":"https://ror.org/01fv1ds98","country_code":"TW","type":"education","lineage":["https://openalex.org/I99908691"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsin-Hung Liu","raw_affiliation_strings":["Department of Computer Science and Engineering, Yuan Ze University Chung-Li, Taiwan","Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Yuan Ze University Chung-Li, Taiwan","institution_ids":["https://openalex.org/I99908691"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan","institution_ids":["https://openalex.org/I99908691"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111898552","display_name":"Rung-Bin Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I99908691","display_name":"Yuan Ze University","ror":"https://ror.org/01fv1ds98","country_code":"TW","type":"education","lineage":["https://openalex.org/I99908691"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Rung-Bin Lin","raw_affiliation_strings":["Department of Computer Science and Engineering, Yuan Ze University Chung-Li, Taiwan","Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Yuan Ze University Chung-Li, Taiwan","institution_ids":["https://openalex.org/I99908691"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan","institution_ids":["https://openalex.org/I99908691"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071885802","display_name":"I-Lun Tseng","orcid":"https://orcid.org/0000-0002-3514-5387"},"institutions":[{"id":"https://openalex.org/I99908691","display_name":"Yuan Ze University","ror":"https://ror.org/01fv1ds98","country_code":"TW","type":"education","lineage":["https://openalex.org/I99908691"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"I-Lun Tseng","raw_affiliation_strings":["Department of Computer Science and Engineering, Yuan Ze University Chung-Li, Taiwan","Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Yuan Ze University Chung-Li, Taiwan","institution_ids":["https://openalex.org/I99908691"]},{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan","institution_ids":["https://openalex.org/I99908691"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6343,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.71942818,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"494","last_page":"501"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9503010511398315},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7700198888778687},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.675503134727478},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5530425906181335},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.5240792632102966},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4561641812324524},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4244164228439331},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3945733904838562},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39130622148513794},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17641499638557434},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08385822176933289},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07855039834976196}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9503010511398315},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7700198888778687},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.675503134727478},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5530425906181335},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.5240792632102966},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4561641812324524},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4244164228439331},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3945733904838562},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39130622148513794},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17641499638557434},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08385822176933289},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07855039834976196},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2013.6523657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2013.6523657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W649343059","https://openalex.org/W1490823210","https://openalex.org/W1503082651","https://openalex.org/W1971495518","https://openalex.org/W1972641423","https://openalex.org/W2094698942","https://openalex.org/W2100094882","https://openalex.org/W2100483769","https://openalex.org/W2106440759","https://openalex.org/W2109887272","https://openalex.org/W2124007645","https://openalex.org/W2125952738","https://openalex.org/W2126287916","https://openalex.org/W2127256196","https://openalex.org/W2128485160","https://openalex.org/W2134697552","https://openalex.org/W2134849712","https://openalex.org/W2162154752","https://openalex.org/W2166135813","https://openalex.org/W2170723854","https://openalex.org/W2270952016","https://openalex.org/W2546087703","https://openalex.org/W3100186937","https://openalex.org/W3139721564","https://openalex.org/W4210458338","https://openalex.org/W4248469525","https://openalex.org/W6684788526","https://openalex.org/W6729448684"],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W4240253816","https://openalex.org/W2170058895","https://openalex.org/W2134697552","https://openalex.org/W2134239612","https://openalex.org/W2383679826","https://openalex.org/W2349682465","https://openalex.org/W1554938446","https://openalex.org/W2041701551"],"abstract_inverted_index":{"Memory":[0],"blocks":[1,21,64,88,132],"in":[2,51],"a":[3,27,38,56,103,124,134],"structured":[4,135],"ASIC":[5],"are":[6],"normally":[7],"pre-customized":[8],"with":[9],"fixed":[10],"sizes":[11],"and":[12,61,76,129],"placed":[13],"at":[14],"predefined":[15],"locations.":[16],"The":[17],"number":[18,126],"of":[19,33,40,89,122,127],"memory":[20,34],"is":[22,114],"also":[23],"pre-determined.":[24],"This":[25],"imposes":[26],"stringent":[28],"limitation":[29],"on":[30,133],"the":[31,66,99,120],"use":[32],"blocks,":[35],"often":[36],"creating":[37],"situation":[39],"either":[41],"insufficient":[42],"capacity":[43],"or":[44],"considerable":[45],"waste.":[46],"To":[47],"remove":[48],"this":[49,52,90,112],"limitation,":[50],"paper":[53],"we":[54],"propose":[55],"method":[57],"to":[58,71,85],"create":[59],"relocatable":[60,128],"resizable":[62,130],"SRAM":[63,78,83,87,94,106,110,131],"using":[65],"same":[67],"via-configurable":[68],"logic":[69,74],"block":[70],"implement":[72],"both":[73],"gates":[75],"6T":[77],"cells.":[79],"We":[80,116],"develop":[81],"an":[82],"compiler":[84],"synthesize":[86],"sort.":[91],"Our":[92],"single-port":[93],"array":[95],"uses":[96],"only":[97],"1/3":[98],"area":[100],"taken":[101],"by":[102],"flip-flop":[104],"based":[105],"array.":[107],"For":[108],"dual-port":[109],"arrays,":[111],"ratio":[113],"2/3.":[115],"demonstrate":[117],"first":[118],"time":[119],"feasibility":[121],"deploying":[123],"varying":[125],"ASIC.":[136]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}