{"id":"https://openalex.org/W2158831994","doi":"https://doi.org/10.1109/isqed.2012.6187505","title":"Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application","display_name":"Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W2158831994","doi":"https://doi.org/10.1109/isqed.2012.6187505","mag":"2158831994"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2012.6187505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041951103","display_name":"Yasumasa Tsukamoto","orcid":"https://orcid.org/0000-0002-0963-6940"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Yasumasa Tsukamoto","raw_affiliation_strings":["Renesas Electronics Corporation, Kodaira, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Electronics Corporation, Kodaira, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088276903","display_name":"Makoto Yabuuchi","orcid":"https://orcid.org/0000-0003-1515-4726"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Yabuuchi","raw_affiliation_strings":["Renesas Electronics Corporation, Kodaira, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Electronics Corporation, Kodaira, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100989173","display_name":"Hidehiro Fujiwara","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hidehiro Fujiwara","raw_affiliation_strings":["Renesas Electronics Corporation, Kodaira, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Electronics Corporation, Kodaira, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047952713","display_name":"Koji Nii","orcid":"https://orcid.org/0000-0002-9986-5308"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Koji Nii","raw_affiliation_strings":["Renesas Electronics Corporation, Kodaira, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Electronics Corporation, Kodaira, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039545794","display_name":"Changhwan Shin","orcid":"https://orcid.org/0000-0001-6057-3773"},"institutions":[{"id":"https://openalex.org/I124633538","display_name":"University of Seoul","ror":"https://ror.org/05en5nh73","country_code":"KR","type":"education","lineage":["https://openalex.org/I124633538"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Changhwan Shin","raw_affiliation_strings":["ECE Department, University of Seoul, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"ECE Department, University of Seoul, Seoul, South Korea","institution_ids":["https://openalex.org/I124633538"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039334041","display_name":"Tsu\u2010Jae King Liu","orcid":"https://orcid.org/0000-0002-1221-2540"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tsu-Jae King Liu","raw_affiliation_strings":["EECS Department, University of California Berkeley, Berkeley, CA, USA"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of California Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5041951103"],"corresponding_institution_ids":["https://openalex.org/I4210153176"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16387778,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"270","last_page":"274"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/shallow-trench-isolation","display_name":"Shallow trench isolation","score":0.7819638252258301},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7284854054450989},{"id":"https://openalex.org/keywords/planar","display_name":"Planar","score":0.7241896390914917},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6999136209487915},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.6310213804244995},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.6053279638290405},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.47732430696487427},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4532696604728699},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.4488907754421234},{"id":"https://openalex.org/keywords/trench","display_name":"Trench","score":0.3778838515281677},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3569408059120178},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.346196711063385},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.2558134198188782},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.24456167221069336},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.20477843284606934},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1884220838546753},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17571699619293213},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.12907305359840393}],"concepts":[{"id":"https://openalex.org/C105066941","wikidata":"https://www.wikidata.org/wiki/Q1424524","display_name":"Shallow trench isolation","level":4,"score":0.7819638252258301},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7284854054450989},{"id":"https://openalex.org/C134786449","wikidata":"https://www.wikidata.org/wiki/Q3391255","display_name":"Planar","level":2,"score":0.7241896390914917},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6999136209487915},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.6310213804244995},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.6053279638290405},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.47732430696487427},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4532696604728699},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.4488907754421234},{"id":"https://openalex.org/C155310634","wikidata":"https://www.wikidata.org/wiki/Q1852785","display_name":"Trench","level":3,"score":0.3778838515281677},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3569408059120178},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.346196711063385},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.2558134198188782},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.24456167221069336},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.20477843284606934},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1884220838546753},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17571699619293213},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.12907305359840393},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2012.6187505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309411","display_name":"University of California Berkeley","ror":"https://ror.org/01an7q238"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1549072435","https://openalex.org/W1970601044","https://openalex.org/W2086328585","https://openalex.org/W2088270758","https://openalex.org/W2121406324","https://openalex.org/W2145100945","https://openalex.org/W2149956781","https://openalex.org/W2161755090","https://openalex.org/W2161934647","https://openalex.org/W2168101540","https://openalex.org/W2738467824","https://openalex.org/W4231296481"],"related_works":["https://openalex.org/W2006928005","https://openalex.org/W2119814266","https://openalex.org/W2749871982","https://openalex.org/W2104314732","https://openalex.org/W2140756430","https://openalex.org/W2188624265","https://openalex.org/W1992381812","https://openalex.org/W1869246841","https://openalex.org/W2006469970","https://openalex.org/W1507517533"],"abstract_inverted_index":{"Quasi-Planar":[0],"Tri-gate":[1],"(QPT)":[2],"Bulk":[3],"MOSFETs":[4],"are":[5],"fabricated":[6],"simply":[7],"by":[8,49],"slightly":[9],"recessing":[10],"the":[11],"shallow":[12],"trench":[13],"isolation":[14],"(STI)":[15],"oxide":[16],"prior":[17],"to":[18,59,70],"gate-stack":[19],"formation.":[20],"In":[21],"this":[22],"cost-effective":[23],"manner,":[24],"7%":[25],"higher":[26],"performance":[27],"with":[28],"lower":[29],"leakage":[30],"current":[31],"in":[32,64],"QPT":[33,68],"bulk":[34,38],"devices":[35],"(vs.":[36],"planar":[37],"devices)":[39],"is":[40],"achieved.":[41],"QPT-based":[42],"single-port":[43],"SRAM":[44],"characteristics":[45],"can":[46],"be":[47],"improved":[48],"employing":[50],"circuit":[51],"design":[52],"techniques":[53],"(i.e.,":[54],"read-":[55],"and":[56],"write-assist":[57],"circuitry)":[58],"compensate":[60],"for":[61],"unequal":[62],"improvements":[63],"n-channel":[65],"vs.":[66],"p-channel":[67],"devices,":[69],"improve":[71],"cell":[72],"yield.":[73]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}