{"id":"https://openalex.org/W2165816612","doi":"https://doi.org/10.1109/isqed.2012.6187503","title":"Process variation aware DRAM design using block based adaptive body biasing algorithm","display_name":"Process variation aware DRAM design using block based adaptive body biasing algorithm","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W2165816612","doi":"https://doi.org/10.1109/isqed.2012.6187503","mag":"2165816612"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2012.6187503","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069566408","display_name":"Satyajit Desai","orcid":null},"institutions":[{"id":"https://openalex.org/I121980950","display_name":"Utah State University","ror":"https://ror.org/00h6set76","country_code":"US","type":"education","lineage":["https://openalex.org/I121980950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satyajit Desai","raw_affiliation_strings":["Electrical and Computer Engineering, Utah State University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Utah State University, USA","institution_ids":["https://openalex.org/I121980950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068885938","display_name":"Sanghamitra Roy","orcid":"https://orcid.org/0000-0002-3927-1612"},"institutions":[{"id":"https://openalex.org/I121980950","display_name":"Utah State University","ror":"https://ror.org/00h6set76","country_code":"US","type":"education","lineage":["https://openalex.org/I121980950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanghamitra Roy","raw_affiliation_strings":["Electrical and Computer Engineering, Utah State University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Utah State University, USA","institution_ids":["https://openalex.org/I121980950"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101594477","display_name":"Koushik Chakraborty","orcid":"https://orcid.org/0000-0003-0228-2737"},"institutions":[{"id":"https://openalex.org/I121980950","display_name":"Utah State University","ror":"https://ror.org/00h6set76","country_code":"US","type":"education","lineage":["https://openalex.org/I121980950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Koushik Chakraborty","raw_affiliation_strings":["Electrical and Computer Engineering, Utah State University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Utah State University, USA","institution_ids":["https://openalex.org/I121980950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7495,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.76393612,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"20","issue":null,"first_page":"255","last_page":"261"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.931453287601471},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.8457704782485962},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6461992263793945},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.5927881598472595},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.5788688063621521},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.46696168184280396},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.441715806722641},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4091606140136719},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.40313494205474854},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3499552607536316},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3408103585243225},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18512862920761108},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.14495405554771423},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1273554563522339},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.1272512972354889}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.931453287601471},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.8457704782485962},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6461992263793945},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.5927881598472595},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.5788688063621521},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.46696168184280396},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.441715806722641},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4091606140136719},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.40313494205474854},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3499552607536316},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3408103585243225},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18512862920761108},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.14495405554771423},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1273554563522339},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.1272512972354889},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2012.6187503","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2012.6187503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Thirteenth International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W612784192","https://openalex.org/W1693570377","https://openalex.org/W2048508570","https://openalex.org/W2099142412","https://openalex.org/W2119081900","https://openalex.org/W2119302817","https://openalex.org/W2132621842","https://openalex.org/W2135956512","https://openalex.org/W2150283124","https://openalex.org/W2150526221","https://openalex.org/W2160980152","https://openalex.org/W2178225970","https://openalex.org/W3145747011","https://openalex.org/W4242819225","https://openalex.org/W6637338991","https://openalex.org/W6677815402","https://openalex.org/W6681979597","https://openalex.org/W6683560071"],"related_works":["https://openalex.org/W4386903460","https://openalex.org/W1643962617","https://openalex.org/W2536264121","https://openalex.org/W2268596372","https://openalex.org/W2338545698","https://openalex.org/W2516517078","https://openalex.org/W4382618825","https://openalex.org/W2900372418","https://openalex.org/W2924367614","https://openalex.org/W4221167253"],"abstract_inverted_index":{"Large":[0],"dense":[1],"structures":[2],"like":[3,63],"DRAMs":[4,39,103],"are":[5],"particularly":[6],"susceptible":[7],"to":[8,14,35,49,150,181,218],"process":[9,50,96,142,155,223],"variation,":[10],"which":[11],"can":[12],"lead":[13],"variable":[15],"latencies":[16],"in":[17,29,102,108,131,203],"different":[18],"memory":[19,70],"arrays.":[20,229],"However,":[21,59],"very":[22],"little":[23],"work":[24],"exists":[25],"on":[26,157,191,225],"variation":[27,51,97,130,143,156,224],"studies":[28],"the":[30,36,55,122,152,158,183,204,208,215,220],"DRAM.":[31],"This":[32,94],"is":[33,214],"due":[34,48],"fact":[37],"that":[38,104],"were":[40],"traditionally":[41],"placed":[42],"off-chip":[43],"and":[44,72,110,161],"their":[45],"latency":[46],"changes":[47],"did":[52],"not":[53],"impact":[54,153,221],"overall":[56],"processor":[57],"performance.":[58],"emerging":[60],"technology":[61,76,85,112],"trends":[62],"three":[64],"dimensional":[65],"integration,":[66],"use":[67,137],"of":[68,75,91,124,154,185,200,210,222],"sophisticated":[69],"controllers":[71],"continued":[73],"scaling":[74],"nodes,":[77],"substantially":[78],"reduces":[79],"DRAM":[80,133,159,186,194,205,228],"access":[81],"latency.":[82],"Hence":[83],"future":[84],"nodes":[86],"will":[87],"see":[88],"widespread":[89],"adoption":[90],"embedded":[92],"DRAMs.":[93],"makes":[95],"a":[98,167,192],"critical":[99],"upcoming":[100],"challenge":[101],"must":[105],"be":[106],"addressed":[107],"current":[109],"forthcoming":[111],"generations.":[113],"In":[114],"this":[115],"paper,":[116],"we":[117,196],"present":[118],"techniques":[119],"for":[120],"modeling":[121],"effect":[123],"random":[125],"as":[126,128],"well":[127],"spatial":[129],"large":[132,226],"array":[134],"structures.":[135,187],"We":[136,164],"sensitivity":[138],"based":[139,170],"gate":[140],"level":[141],"models":[144],"combined":[145],"with":[146],"statistical":[147],"timing":[148],"analysis":[149],"estimate":[151],"performance":[160],"leakage":[162],"power.":[163],"also":[165],"propose":[166],"simulated":[168],"annealing":[169],"V":[171],"<sub":[172],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[173],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</sub>":[174],"assignment":[175],"algorithm":[176,190],"using":[177],"adaptive":[178],"body":[179],"biasing":[180],"improve":[182],"yield":[184],"Applying":[188],"our":[189,211],"1GB":[193],"array,":[195],"report":[197],"an":[198],"average":[199],"10.3%":[201],"improvement":[202],"yield.":[206],"To":[207],"best":[209],"knowledge,":[212],"ours":[213],"first":[216],"technique":[217],"model":[219],"scale":[227]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}