{"id":"https://openalex.org/W2138851610","doi":"https://doi.org/10.1109/isqed.2011.5770816","title":"Constructive AIG optimization considering input weights","display_name":"Constructive AIG optimization considering input weights","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2138851610","doi":"https://doi.org/10.1109/isqed.2011.5770816","mag":"2138851610"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770816","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770816","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031810932","display_name":"Thiago Figueiro","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Thiago Figueiro","raw_affiliation_strings":["Instituto de Inform\u00e1tica-UFRGS, PGMICRO, Porto Alegre, Rio Grande do Sul, Brazil","PGMICRO - Instituto de Inform\u00e1tica - UFRGS, Porto Alegre/RS, Brazil"],"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica-UFRGS, PGMICRO, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PGMICRO - Instituto de Inform\u00e1tica - UFRGS, Porto Alegre/RS, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato Perez Ribas","raw_affiliation_strings":["Instituto de Inform\u00e1tica-UFRGS, PGMICRO, Porto Alegre, Rio Grande do Sul, Brazil","PGMICRO - Instituto de Inform\u00e1tica - UFRGS, Porto Alegre/RS, Brazil"],"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica-UFRGS, PGMICRO, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PGMICRO - Instituto de Inform\u00e1tica - UFRGS, Porto Alegre/RS, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andre Inacio Reis","raw_affiliation_strings":["Instituto de Inform\u00e1tica-UFRGS, PGMICRO, Porto Alegre, Rio Grande do Sul, Brazil","PGMICRO - Instituto de Inform\u00e1tica - UFRGS, Porto Alegre/RS, Brazil"],"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica-UFRGS, PGMICRO, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"PGMICRO - Instituto de Inform\u00e1tica - UFRGS, Porto Alegre/RS, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5031810932"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":0.7949,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.76961767,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7034227252006531},{"id":"https://openalex.org/keywords/constructive","display_name":"Constructive","score":0.6043257117271423},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5699683427810669},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4426553249359131},{"id":"https://openalex.org/keywords/graph-theory","display_name":"Graph theory","score":0.42050057649612427},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.41667795181274414},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3550567626953125},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3506428599357605},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.32439905405044556},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32009485363960266},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17669269442558289},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.1007612943649292},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09934437274932861},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08428823947906494}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7034227252006531},{"id":"https://openalex.org/C2778701210","wikidata":"https://www.wikidata.org/wiki/Q28130034","display_name":"Constructive","level":3,"score":0.6043257117271423},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5699683427810669},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4426553249359131},{"id":"https://openalex.org/C88230418","wikidata":"https://www.wikidata.org/wiki/Q131476","display_name":"Graph theory","level":2,"score":0.42050057649612427},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.41667795181274414},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3550567626953125},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3506428599357605},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.32439905405044556},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32009485363960266},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17669269442558289},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.1007612943649292},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09934437274932861},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08428823947906494},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770816","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770816","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1505590927","https://openalex.org/W1511688816","https://openalex.org/W1612810659","https://openalex.org/W1985457698","https://openalex.org/W2015987974","https://openalex.org/W2060940692","https://openalex.org/W2100465945","https://openalex.org/W2105715355","https://openalex.org/W2106323499","https://openalex.org/W2110271570","https://openalex.org/W2137753585","https://openalex.org/W2155702064","https://openalex.org/W2294502317","https://openalex.org/W2405074492","https://openalex.org/W2520093650","https://openalex.org/W3151084440","https://openalex.org/W6630623413","https://openalex.org/W6636505876","https://openalex.org/W6675210143","https://openalex.org/W6682910769","https://openalex.org/W6697174721","https://openalex.org/W6713493740"],"related_works":["https://openalex.org/W4311883357","https://openalex.org/W2377770720","https://openalex.org/W2113626999","https://openalex.org/W160889949","https://openalex.org/W2364696089","https://openalex.org/W309910862","https://openalex.org/W4210637712","https://openalex.org/W2369004811","https://openalex.org/W2392500469","https://openalex.org/W2762831627"],"abstract_inverted_index":{"This":[0,77],"work":[1],"presents":[2],"a":[3,86,94,113],"technology":[4],"independent":[5],"synthesis":[6,96,107],"algorithm":[7],"that":[8],"works":[9],"on":[10,93],"top":[11],"of":[12,26,31,64,82,121,129,136],"an":[13],"And-Inverter":[14],"Graph":[15],"(AIG)":[16],"data":[17],"structure.":[18],"The":[19,101,116],"goal":[20],"is":[21,54,103],"to":[22,56,60,69,85,104],"minimize":[23],"the":[24,29,32,40,61,65,80,106,127,134],"number":[25,135],"nodes":[27,63,138],"and":[28,123],"depth":[30],"AIG,":[33],"by":[34,108],"controlling":[35],"these":[36],"characteristics":[37,120],"while":[38],"building":[39],"graph.":[41],"Moreover,":[42],"large":[43],"circuits":[44],"are":[45],"usually":[46],"synthesized":[47],"in":[48,67,112],"stages":[49],"(cuts)":[50],"and,":[51],"therefore,":[52],"it":[53],"desirable":[55],"consider":[57],"different":[58],"weights":[59,84],"input":[62,83],"AIGs":[66],"order":[68],"represent":[70],"signal":[71],"delay":[72],"from":[73],"previous":[74],"circuit":[75],"stages.":[76],"paper":[78],"incorporates":[79],"employ":[81],"novel":[87],"approach":[88],"for":[89,139],"AIG":[90,137],"construction":[91],"based":[92],"new":[95],"paradigm":[97],"called":[98],"functional":[99],"composition.":[100],"idea":[102],"perform":[105],"associating":[109],"simpler":[110],"AIGs,":[111],"bottom-up":[114],"approach.":[115],"method":[117],"constructively":[118],"controls":[119],"final":[122],"intermediate":[124],"graphs,":[125],"allowing":[126],"adoption":[128],"secondary":[130],"criteria":[131],"other":[132],"than":[133],"optimization.":[140]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}