{"id":"https://openalex.org/W2156049234","doi":"https://doi.org/10.1109/isqed.2011.5770797","title":"Gridless wire ordering, sizing and spacing with critical area minimization","display_name":"Gridless wire ordering, sizing and spacing with critical area minimization","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2156049234","doi":"https://doi.org/10.1109/isqed.2011.5770797","mag":"2156049234"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770797","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770797","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025042501","display_name":"Yu\u2010Wei Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yu-Wei Lee","raw_affiliation_strings":["Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102859957","display_name":"Yen\u2010Hung Lin","orcid":"https://orcid.org/0000-0001-6819-1235"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen-Hung Lin","raw_affiliation_strings":["Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034618339","display_name":"Yih-Lang Li","orcid":"https://orcid.org/0000-0002-6441-2392"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yih-Lang Li","raw_affiliation_strings":["Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5025042501"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1653088,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"11","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7559932470321655},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7146665453910828},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.658485472202301},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5664666295051575},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.53961181640625},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.493142306804657},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4662182927131653},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.436741441488266},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2461976408958435},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22493991255760193},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.0824979841709137}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7559932470321655},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7146665453910828},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.658485472202301},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5664666295051575},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.53961181640625},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.493142306804657},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4662182927131653},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.436741441488266},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2461976408958435},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22493991255760193},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0824979841709137},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770797","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770797","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1761548667","https://openalex.org/W1975577567","https://openalex.org/W1998976901","https://openalex.org/W2023051081","https://openalex.org/W2049967610","https://openalex.org/W2070232376","https://openalex.org/W2103241566","https://openalex.org/W2107973438","https://openalex.org/W2110169477","https://openalex.org/W2129736362","https://openalex.org/W2129999950","https://openalex.org/W2132915653","https://openalex.org/W2154308245","https://openalex.org/W2154526391","https://openalex.org/W2172669402","https://openalex.org/W2186223162","https://openalex.org/W3146313257","https://openalex.org/W3146788732","https://openalex.org/W4255326129","https://openalex.org/W6643977565","https://openalex.org/W6682362610"],"related_works":["https://openalex.org/W2055240106","https://openalex.org/W1518650219","https://openalex.org/W2005452361","https://openalex.org/W4234353339","https://openalex.org/W2113275738","https://openalex.org/W2046102945","https://openalex.org/W4240503776","https://openalex.org/W1919516409","https://openalex.org/W1693171640","https://openalex.org/W2167693349"],"abstract_inverted_index":{"Designs":[0],"for":[1,24,123],"yield":[2],"(DFY)":[3],"problems":[4,14],"have":[5,44],"received":[6],"increasing":[7],"attention.":[8],"Of":[9],"particular":[10],"concern":[11],"in":[12,98,139,220],"DFY":[13],"is":[15,29,104],"how":[16],"to":[17,61,81,106,110,127,196,213,227],"formulate":[18],"and":[19,52,58,65,76,96,125,161,177],"reduce":[20],"a":[21,70,111,119,147],"critical":[22],"area":[23],"random":[25,40,47,71,86],"defects.":[26,41,87],"Arranging":[27],"interconnections":[28,51],"recognized":[30],"as":[31,225],"an":[32,154],"effective":[33],"means":[34],"of":[35,55,85,136,163,171,174,185,215,218],"improving":[36],"the":[37,53,83,134,159,169,172,183,186,216,221],"sensitivity":[38],"towards":[39],"Previous":[42],"works":[43,208],"demonstrated":[45],"that":[46],"defects":[48],"significantly":[49],"influence":[50],"effectiveness":[54,184],"layer":[56,74,113,175],"assignment":[57,75,176],"track":[59,78,89,178,188],"routing":[60,63,79,90,189],"enhance":[62],"quality":[64],"performance.":[66],"This":[67],"work":[68],"proposes":[69],"defect":[72],"aware":[73],"gridless":[77,187],"(RAAT)":[80],"eliminate":[82],"effect":[84,157],"Gridless":[88],"comprises":[91],"wire":[92,94,137],"ordering,":[93],"sizing":[95],"spacing":[97],"this":[99],"work.":[100],"Exposure":[101],"ratio":[102],"metric":[103],"proposed":[105,191],"assign":[107],"each":[108,164,198],"iroute":[109],"specific":[112],"efficiently.":[114],"RAAT":[115,210],"utilizes":[116],"min-cut":[117],"partitioning,":[118],"conventionally":[120],"adopted":[121],"method":[122],"placement":[124],"floorplanning,":[126],"place":[128],"interconnections.":[129],"Slicing":[130],"tree-based":[131],"structure":[132],"improves":[133],"efficiency":[135],"ordering":[138],"lowering":[140],"overlapped":[141],"length":[142],"between":[143],"adjacent":[144],"partitions.":[145],"Finally,":[146],"second-order":[148],"cone":[149],"programming":[150],"refined":[151],"by":[152,192],"considering":[153],"extra":[155],"random-defect":[156],"determines":[158],"position":[160],"width":[162],"iroute.":[165],"Experimental":[166],"results":[167],"demonstrate":[168,182],"necessity":[170],"integration":[173],"routing.":[179],"Results":[180],"further":[181],"methods":[190],"RAAT.":[193],"In":[194],"addition":[195],"finishing":[197],"case":[199],"more":[200],"rapidly":[201],"with":[202],"higher":[203],"completion":[204],"rate":[205],"than":[206],"previous":[207,228],"do,":[209],"reduces":[211],"up":[212],"20%":[214],"number":[217],"failures":[219],"Monte":[222],"Carlo":[223],"simulation":[224],"compared":[226],"works.":[229]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
