{"id":"https://openalex.org/W2139571759","doi":"https://doi.org/10.1109/isqed.2011.5770796","title":"The effect of SRNR on timing characteristics of signal busses","display_name":"The effect of SRNR on timing characteristics of signal busses","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2139571759","doi":"https://doi.org/10.1109/isqed.2011.5770796","mag":"2139571759"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770796","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770796","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020087008","display_name":"Bassel Soudan","orcid":"https://orcid.org/0000-0001-8128-5498"},"institutions":[{"id":"https://openalex.org/I29891158","display_name":"University of Sharjah","ror":"https://ror.org/00engpz63","country_code":"AE","type":"education","lineage":["https://openalex.org/I29891158"]}],"countries":["AE"],"is_corresponding":true,"raw_author_name":"Bassel Soudan","raw_affiliation_strings":["University of Sharjah, Sharjah, UAE","University of Sharjah, sharjah, United Arab Emirates"],"affiliations":[{"raw_affiliation_string":"University of Sharjah, Sharjah, UAE","institution_ids":["https://openalex.org/I29891158"]},{"raw_affiliation_string":"University of Sharjah, sharjah, United Arab Emirates","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5020087008"],"corresponding_institution_ids":["https://openalex.org/I29891158"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15693489,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.7447223663330078},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7095113396644592},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.6957932114601135},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6675575375556946},{"id":"https://openalex.org/keywords/capacitive-sensing","display_name":"Capacitive sensing","score":0.6373363733291626},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.6047728061676025},{"id":"https://openalex.org/keywords/capacitive-coupling","display_name":"Capacitive coupling","score":0.5798577070236206},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5774762630462646},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5419008135795593},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.46830880641937256},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3486573100090027},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3295687139034271},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2402772307395935},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20815834403038025},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.18560129404067993},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13912999629974365}],"concepts":[{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.7447223663330078},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7095113396644592},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.6957932114601135},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6675575375556946},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.6373363733291626},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.6047728061676025},{"id":"https://openalex.org/C68278764","wikidata":"https://www.wikidata.org/wiki/Q444167","display_name":"Capacitive coupling","level":3,"score":0.5798577070236206},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5774762630462646},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5419008135795593},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.46830880641937256},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3486573100090027},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3295687139034271},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2402772307395935},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20815834403038025},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.18560129404067993},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13912999629974365},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770796","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770796","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1562592802","https://openalex.org/W1598974075","https://openalex.org/W2050871722","https://openalex.org/W2097056724","https://openalex.org/W2097190067","https://openalex.org/W2097418240","https://openalex.org/W2116404099","https://openalex.org/W2118868896","https://openalex.org/W2119039311","https://openalex.org/W2119302817","https://openalex.org/W2119925363","https://openalex.org/W2132703824","https://openalex.org/W2147963451","https://openalex.org/W2158457122","https://openalex.org/W2165946781","https://openalex.org/W2166230687","https://openalex.org/W2167848093","https://openalex.org/W2281416936","https://openalex.org/W2532868014","https://openalex.org/W3150367143","https://openalex.org/W4230172191","https://openalex.org/W6674274919","https://openalex.org/W6677815402","https://openalex.org/W6684441436"],"related_works":["https://openalex.org/W85694287","https://openalex.org/W1970480028","https://openalex.org/W2287031256","https://openalex.org/W2165357077","https://openalex.org/W2885948601","https://openalex.org/W2162651506","https://openalex.org/W1998400967","https://openalex.org/W4241171805","https://openalex.org/W2020253769","https://openalex.org/W2143930978"],"abstract_inverted_index":{"At":[0],"exceedingly":[1],"high":[2,6],"integration":[3],"nodes":[4],"and":[5,24,31,47,64,90],"signal":[7,10,73,78],"transition":[8],"frequencies,":[9],"integrity":[11],"(SI)":[12],"is":[13,69,88],"a":[14],"major":[15],"design":[16],"concern.":[17],"The":[18,33],"main":[19],"culprits":[20],"are":[21],"parasitics,":[22],"capacitive":[23,46],"inductive,":[25],"inherent":[26],"in":[27,50,76],"the":[28,42,53,85,96],"circuit":[29],"elements":[30],"interconnect.":[32],"Semi-Random":[34],"Net":[35],"Reordering":[36],"(SRNR)":[37],"technique":[38,87],"concentrates":[39],"on":[40],"reducing":[41,61],"fundamental":[43],"contributors":[44],"to":[45,71,95],"inductive":[48],"coupling":[49],"interconnect":[51],"at":[52],"top-level":[54],"of":[55],"an":[56],"integrated":[57],"circuit's":[58],"design.":[59],"By":[60],"overlap":[62],"length":[63],"increasing":[65],"separation":[66],"distance,":[67],"SRNR":[68,86],"able":[70],"improve":[72],"timing":[74],"characteristics":[75],"wide":[77],"busses":[79],"dramatically.":[80],"A":[81],"routing":[82,98,102],"structure":[83,99],"employing":[84],"faster":[89],"more":[91],"uniformly":[92],"behaved":[93],"compared":[94],"same":[97],"under":[100],"standard":[101],"methodology.":[103]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}