{"id":"https://openalex.org/W2103056712","doi":"https://doi.org/10.1109/isqed.2011.5770774","title":"Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools","display_name":"Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2103056712","doi":"https://doi.org/10.1109/isqed.2011.5770774","mag":"2103056712"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770774","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770774","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075763259","display_name":"Sophie Belloeil-Dupuis","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I204730241","display_name":"Universit\u00e9 Paris Cit\u00e9","ror":"https://ror.org/05f82e368","country_code":"FR","type":"education","lineage":["https://openalex.org/I204730241"]},{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"Sophie Belloeil-Dupuis","raw_affiliation_strings":["LIP6/SOC Laboratory, University of Paris-VI, Paris, France","University Paris VI, LIP6/SOC Laboratory, 4 place Jussieu, 75252 Paris Cedex 05, France"],"affiliations":[{"raw_affiliation_string":"LIP6/SOC Laboratory, University of Paris-VI, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I204730241"]},{"raw_affiliation_string":"University Paris VI, LIP6/SOC Laboratory, 4 place Jussieu, 75252 Paris Cedex 05, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110226823","display_name":"Roselyne Chotin-Avot","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I204730241","display_name":"Universit\u00e9 Paris Cit\u00e9","ror":"https://ror.org/05f82e368","country_code":"FR","type":"education","lineage":["https://openalex.org/I204730241"]},{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Roselyne Chotin-Avot","raw_affiliation_strings":["LIP6/SOC Laboratory, University of Paris-VI, Paris, France","University Paris VI, LIP6/SOC Laboratory, 4 place Jussieu, 75252 Paris Cedex 05, France"],"affiliations":[{"raw_affiliation_string":"LIP6/SOC Laboratory, University of Paris-VI, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I204730241"]},{"raw_affiliation_string":"University Paris VI, LIP6/SOC Laboratory, 4 place Jussieu, 75252 Paris Cedex 05, France","institution_ids":["https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108405631","display_name":"Habib Mehrez","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I204730241","display_name":"Universit\u00e9 Paris Cit\u00e9","ror":"https://ror.org/05f82e368","country_code":"FR","type":"education","lineage":["https://openalex.org/I204730241"]},{"id":"https://openalex.org/I4210159731","display_name":"Laboratoire de Recherche en Informatique de Paris 6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Habib Mehrez","raw_affiliation_strings":["LIP6/SOC Laboratory, University of Paris-VI, Paris, France","University Paris VI, LIP6/SOC Laboratory, 4 place Jussieu, 75252 Paris Cedex 05, France"],"affiliations":[{"raw_affiliation_string":"LIP6/SOC Laboratory, University of Paris-VI, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I204730241"]},{"raw_affiliation_string":"University Paris VI, LIP6/SOC Laboratory, 4 place Jussieu, 75252 Paris Cedex 05, France","institution_ids":["https://openalex.org/I39804081"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5075763259"],"corresponding_institution_ids":["https://openalex.org/I204730241","https://openalex.org/I39804081","https://openalex.org/I4210159731"],"apc_list":null,"apc_paid":null,"fwci":0.2588,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.58220323,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8637257218360901},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7857410907745361},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7472376823425293},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7338670492172241},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6512203812599182},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6198711395263672},{"id":"https://openalex.org/keywords/interoperability","display_name":"Interoperability","score":0.6176058650016785},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.5962148308753967},{"id":"https://openalex.org/keywords/python","display_name":"Python (programming language)","score":0.5882397294044495},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5167019367218018},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.504996120929718},{"id":"https://openalex.org/keywords/virtual-prototyping","display_name":"Virtual prototyping","score":0.4553043246269226},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4431871175765991},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4400904178619385},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36065903306007385},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3162271976470947},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1872541308403015},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10116365551948547}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8637257218360901},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7857410907745361},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7472376823425293},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7338670492172241},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6512203812599182},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6198711395263672},{"id":"https://openalex.org/C20136886","wikidata":"https://www.wikidata.org/wiki/Q749647","display_name":"Interoperability","level":2,"score":0.6176058650016785},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.5962148308753967},{"id":"https://openalex.org/C519991488","wikidata":"https://www.wikidata.org/wiki/Q28865","display_name":"Python (programming language)","level":2,"score":0.5882397294044495},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5167019367218018},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.504996120929718},{"id":"https://openalex.org/C2780991453","wikidata":"https://www.wikidata.org/wiki/Q3408177","display_name":"Virtual prototyping","level":2,"score":0.4553043246269226},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4431871175765991},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4400904178619385},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36065903306007385},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3162271976470947},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1872541308403015},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10116365551948547},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/isqed.2011.5770774","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770774","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-01265627v1","is_oa":false,"landing_page_url":"https://hal.sorbonne-universite.fr/hal-01265627","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISQED 2011 - 12th International Symposium on Quality Electronic Design, Mar 2011, Santa Clara, CA, United States. pp.502-507, &#x27E8;10.1109/ISQED.2011.5770774&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1560795149","https://openalex.org/W1986396242","https://openalex.org/W2113534968","https://openalex.org/W2120549874","https://openalex.org/W2138342018","https://openalex.org/W2139286713","https://openalex.org/W2153206520","https://openalex.org/W2162654200","https://openalex.org/W2170375420","https://openalex.org/W2624409640","https://openalex.org/W6633740673","https://openalex.org/W6646754854","https://openalex.org/W6684631565","https://openalex.org/W6739144586"],"related_works":["https://openalex.org/W1903431847","https://openalex.org/W2110818533","https://openalex.org/W2166021916","https://openalex.org/W1917852300","https://openalex.org/W2079896081","https://openalex.org/W4236123807","https://openalex.org/W1843355381","https://openalex.org/W1492116303","https://openalex.org/W2069295582","https://openalex.org/W2077870657"],"abstract_inverted_index":{"Stratus":[0,46],"is":[1],"an":[2],"open-source":[3],"language":[4],"based":[5],"upon":[6],"Python":[7],"dedicated":[8],"to":[9],"the":[10],"generation":[11],"of":[12,24,54],"VLSI":[13],"modules.":[14],"It":[15,28],"allows":[16],"design":[17],"reuse,":[18],"by":[19],"providing":[20],"a":[21,48],"virtual":[22],"library":[23],"configurable":[25],"IP":[26],"blocks.":[27],"provides":[29,47],"also":[30],"optimization":[31],"techniques":[32],"that":[33],"can":[34],"be":[35],"applied":[36],"during":[37],"datapath":[38],"synthesis.":[39],"In":[40],"this":[41],"paper,":[42],"we":[43],"present":[44],"how":[45],"programming":[49],"framework":[50],"allowing":[51],"fast":[52],"prototyping":[53],"parametrized":[55],"Digital":[56],"Signal":[57],"Processing":[58],"applications,":[59],"ASIC":[60],"or":[61],"FPGA-targeted.":[62]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2016-06-24T00:00:00"}
