{"id":"https://openalex.org/W2036706596","doi":"https://doi.org/10.1109/isqed.2011.5770772","title":"Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration","display_name":"Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2036706596","doi":"https://doi.org/10.1109/isqed.2011.5770772","mag":"2036706596"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007001727","display_name":"Anirban Sengupta","orcid":"https://orcid.org/0000-0002-8215-7903"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Anirban Sengupta","raw_affiliation_strings":["Electrical and Computer Engineering, Ryerson University, Toronto, Canada","Electrical and Computer Engineering, Ryerson University, Toronto, M5B 2K3, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]},{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University, Toronto, M5B 2K3, Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101714993","display_name":"Reza Sedaghat","orcid":"https://orcid.org/0000-0003-0023-7131"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Reza Sedaghat","raw_affiliation_strings":["Electrical and Computer Engineering, Ryerson University, Toronto, Canada","Electrical and Computer Engineering, Ryerson University, Toronto, M5B 2K3, Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]},{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University, Toronto, M5B 2K3, Canada","institution_ids":["https://openalex.org/I530967"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5007001727"],"corresponding_institution_ids":["https://openalex.org/I530967"],"apc_list":null,"apc_paid":null,"fwci":1.93343649,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.87212156,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.749416708946228},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6039965748786926},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5831099152565002},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5494080781936646},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5361487865447998},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49049991369247437},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.48556944727897644},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.46230900287628174},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41573649644851685},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.3627815842628479},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.33300459384918213},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.32076770067214966},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3018287420272827},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.26731759309768677},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.22849559783935547},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11309629678726196}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.749416708946228},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6039965748786926},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5831099152565002},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5494080781936646},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5361487865447998},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49049991369247437},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.48556944727897644},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.46230900287628174},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41573649644851685},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.3627815842628479},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.33300459384918213},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.32076770067214966},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3018287420272827},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26731759309768677},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.22849559783935547},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11309629678726196},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1964698923","https://openalex.org/W1964978749","https://openalex.org/W1980587820","https://openalex.org/W2071550127","https://openalex.org/W2087765167","https://openalex.org/W2102510699","https://openalex.org/W2105742976","https://openalex.org/W2113962082","https://openalex.org/W2119674509","https://openalex.org/W2121863986","https://openalex.org/W2122941519","https://openalex.org/W2129183345","https://openalex.org/W2131065168","https://openalex.org/W2131641949","https://openalex.org/W2140669431","https://openalex.org/W2149449941","https://openalex.org/W2168010321","https://openalex.org/W2171318521","https://openalex.org/W3150996524","https://openalex.org/W4240544559","https://openalex.org/W6679545468"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2269990635","https://openalex.org/W2612099726","https://openalex.org/W2108242004","https://openalex.org/W4312985392","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W4281784598","https://openalex.org/W4313484792","https://openalex.org/W2619340758"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,74,88,167],"novel":[4,46,89],"multi":[5],"structure":[6],"genetic":[7],"algorithm":[8],"based":[9,29,49,170],"design":[10],"space":[11],"exploration":[12,68],"system":[13],"which":[14,93],"concurrently":[15],"solves":[16],"the":[17,31,67,79,96,107,118,122,134,139,146],"problem":[18],"of":[19,106,117,124,158],"integrated":[20],"scheduling,":[21],"allocation":[22],"and":[23,36,53,62,112,131,145],"binding":[24],"in":[25,104],"High":[26],"Level":[27],"Synthesis":[28],"on":[30,50],"user":[32,108],"specified":[33,109],"power":[34,51,113,143],"consumption":[35,52,144],"execution":[37,54,110,141],"time":[38,55,111],"constraints":[39],"(not":[40],"just":[41],"latency":[42],"constraint).":[43],"The":[44,70,115,151],"proposed":[45,152],"cost":[47],"function":[48],"considers":[56],"functional":[57],"units,":[58],"registers,":[59],"multiplexers,":[60,129],"demultiplexers":[61,130],"clock":[63,127],"frequency":[64],"oscillator":[65],"during":[66],"process.":[69],"presented":[71],"approach":[72,153],"incorporates":[73],"new":[75],"seeding":[76],"process":[77],"for":[78,156],"two":[80],"special":[81],"parent":[82],"chromosomes":[83],"as":[84,86],"well":[85],"employs":[87],"`load":[90],"factor":[91],"heuristic'":[92],"guarantees":[94],"that":[95],"final":[97,119,135],"solution":[98,120],"found":[99],"will":[100],"always":[101],"be":[102],"optimal/near-optimal":[103,147],"terms":[105],"constraints.":[114],"results":[116,164],"reflect":[121],"number":[123,157],"adders/subtractors,":[125],"multipliers,":[126],"frequency,":[128],"registers.":[132],"Further,":[133],"result":[136],"also":[137],"indicates":[138],"latency,":[140],"time,":[142],"resource":[148],"combination":[149],"found.":[150],"when":[154],"verified":[155],"standard":[159],"DSP":[160],"benchmarks":[161],"yielded":[162],"superior":[163],"compared":[165],"to":[166],"recent":[168],"GA":[169],"heuristic":[171],"approach.":[172]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}