{"id":"https://openalex.org/W2132731499","doi":"https://doi.org/10.1109/isqed.2011.5770769","title":"Automatic post-layout flow validation tool for Deep Sub-micron process design kits","display_name":"Automatic post-layout flow validation tool for Deep Sub-micron process design kits","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2132731499","doi":"https://doi.org/10.1109/isqed.2011.5770769","mag":"2132731499"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770769","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055300991","display_name":"Pinping Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pinping Sun","raw_affiliation_strings":["IBM, Hopewell Junction, NY, USA","IBM, 2070 Rt 52, Hopewell Junction, NY"],"affiliations":[{"raw_affiliation_string":"IBM, Hopewell Junction, NY, USA","institution_ids":["https://openalex.org/I1341412227"]},{"raw_affiliation_string":"IBM, 2070 Rt 52, Hopewell Junction, NY","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068352386","display_name":"Cole Zemke","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210134083","display_name":"Essex Westford School District","ror":"https://ror.org/03ze2q110","country_code":"US","type":"education","lineage":["https://openalex.org/I4210134083"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cole Zemke","raw_affiliation_strings":["IBM, Essex Junction, VT, USA","IBM, 1000 River St., Essex Junction, VT"],"affiliations":[{"raw_affiliation_string":"IBM, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I4210134083"]},{"raw_affiliation_string":"IBM, 1000 River St., Essex Junction, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082957730","display_name":"Wayne Woods","orcid":null},"institutions":[{"id":"https://openalex.org/I4210134083","display_name":"Essex Westford School District","ror":"https://ror.org/03ze2q110","country_code":"US","type":"education","lineage":["https://openalex.org/I4210134083"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wayne H. Woods","raw_affiliation_strings":["IBM, Essex Junction, VT, USA","IBM, 1000 River St., Essex Junction, VT"],"affiliations":[{"raw_affiliation_string":"IBM, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I4210134083"]},{"raw_affiliation_string":"IBM, 1000 River St., Essex Junction, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033836455","display_name":"Nick Perez","orcid":null},"institutions":[{"id":"https://openalex.org/I4210134083","display_name":"Essex Westford School District","ror":"https://ror.org/03ze2q110","country_code":"US","type":"education","lineage":["https://openalex.org/I4210134083"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nick Perez","raw_affiliation_strings":["IBM, Essex Junction, VT, USA","IBM, 1000 River St., Essex Junction, VT"],"affiliations":[{"raw_affiliation_string":"IBM, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I4210134083"]},{"raw_affiliation_string":"IBM, 1000 River St., Essex Junction, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100330273","display_name":"Yi Li","orcid":"https://orcid.org/0000-0001-9292-8604"},"institutions":[{"id":"https://openalex.org/I4210134083","display_name":"Essex Westford School District","ror":"https://ror.org/03ze2q110","country_code":"US","type":"education","lineage":["https://openalex.org/I4210134083"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hailing Wang","raw_affiliation_strings":["IBM, Essex Junction, VT, USA","IBM, 1000 River St., Essex Junction, VT"],"affiliations":[{"raw_affiliation_string":"IBM, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I4210134083"]},{"raw_affiliation_string":"IBM, 1000 River St., Essex Junction, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041043900","display_name":"Essam Mina","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},{"id":"https://openalex.org/I4210134083","display_name":"Essex Westford School District","ror":"https://ror.org/03ze2q110","country_code":"US","type":"education","lineage":["https://openalex.org/I4210134083"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Essam Mina","raw_affiliation_strings":["IBM, Essex Junction, VT, USA","IBM, 1000 River St., Essex Junction, VT"],"affiliations":[{"raw_affiliation_string":"IBM, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I4210134083"]},{"raw_affiliation_string":"IBM, 1000 River St., Essex Junction, VT","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051117706","display_name":"Barbara Dewitt","orcid":null},"institutions":[{"id":"https://openalex.org/I4210134083","display_name":"Essex Westford School District","ror":"https://ror.org/03ze2q110","country_code":"US","type":"education","lineage":["https://openalex.org/I4210134083"]},{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Barbara Dewitt","raw_affiliation_strings":["IBM, Essex Junction, VT, USA","IBM, 1000 River St., Essex Junction, VT"],"affiliations":[{"raw_affiliation_string":"IBM, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I4210134083"]},{"raw_affiliation_string":"IBM, 1000 River St., Essex Junction, VT","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5055300991"],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15767872,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.8236429691314697},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6759423613548279},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6748400926589966},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6491347551345825},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.6278337836265564},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.5999040603637695},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5131693482398987},{"id":"https://openalex.org/keywords/flow","display_name":"Flow (mathematics)","score":0.49271300435066223},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4912561774253845},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4521196484565735},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44774138927459717},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4410555362701416},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4314590394496918},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.42557936906814575},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41798773407936096},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.40433356165885925},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.301552414894104},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22686225175857544},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19630327820777893},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19081541895866394},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13760918378829956}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.8236429691314697},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6759423613548279},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6748400926589966},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6491347551345825},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.6278337836265564},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.5999040603637695},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5131693482398987},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.49271300435066223},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4912561774253845},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4521196484565735},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44774138927459717},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4410555362701416},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4314590394496918},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.42557936906814575},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41798773407936096},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.40433356165885925},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.301552414894104},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22686225175857544},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19630327820777893},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19081541895866394},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13760918378829956},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770769","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770769","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1560077125","https://openalex.org/W1994905616","https://openalex.org/W2070111044","https://openalex.org/W2098819354","https://openalex.org/W2117330264","https://openalex.org/W2169730278"],"related_works":["https://openalex.org/W2743305891","https://openalex.org/W2051886008","https://openalex.org/W2535520145","https://openalex.org/W1716153929","https://openalex.org/W4247760676","https://openalex.org/W3205162826","https://openalex.org/W4321510758","https://openalex.org/W3199828306","https://openalex.org/W1999810416","https://openalex.org/W2223186343"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3],"novel":[4],"automated":[5,93],"post-layout":[6,94],"flow":[7,95],"validation":[8,96],"tool":[9],"to":[10,73],"intensively":[11],"test":[12,54,68],"the":[13,58,61,66,75,92,99,103],"MOSFETs":[14],"and":[15,21,35,48,77,82,101],"passive":[16,36],"components":[17],"in":[18,50],"32nm,":[19],"28nm":[20],"22nm":[22],"Process":[23],"Design":[24],"Kits":[25],"(PDK).":[26],"Benchmark":[27],"circuits,":[28,38],"such":[29],"as,":[30],"ring":[31],"oscillator,":[32],"logic":[33],"circuits":[34],"delay":[37,62],"are":[39,70],"automatically":[40],"generated,":[41],"LVS":[42,81],"(layout":[43],"versus":[44],"schematic)":[45],"checked,":[46],"extracted":[47],"simulated":[49],"multiple":[51],"Model/LVS/Parasitic":[52],"extraction(PEX)":[53],"flows.":[55],"By":[56],"using":[57],"proposed":[59],"tool,":[60],"differences":[63],"(deltas)":[64],"between":[65],"different":[67],"flows":[69],"cross":[71],"verified":[72],"assure":[74],"functionality":[76],"accuracy":[78],"of":[79,106],"Model,":[80],"PEX":[83],"before":[84],"PDK":[85],"release.":[86],"Combined":[87],"with":[88],"field":[89],"solver":[90],"validation,":[91],"significantly":[97],"improves":[98],"quality":[100],"reduces":[102],"development":[104],"time":[105],"Deep":[107],"Submicron":[108],"(DSM)":[109],"PDKs.":[110]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
