{"id":"https://openalex.org/W2095769627","doi":"https://doi.org/10.1109/isqed.2011.5770758","title":"Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling","display_name":"Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2095769627","doi":"https://doi.org/10.1109/isqed.2011.5770758","mag":"2095769627"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770758","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044487544","display_name":"Oleg Garitselov","orcid":null},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Oleg Garitselov","raw_affiliation_strings":["NanoSystem Design Laboratory, University of North Texas, Denton, TX, USA","NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"NanoSystem Design Laboratory, University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070359867","display_name":"Saraju P. Mohanty","orcid":"https://orcid.org/0000-0003-2959-6541"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saraju P. Mohanty","raw_affiliation_strings":["NanoSystem Design Laboratory, University of North Texas, Denton, TX, USA","NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"NanoSystem Design Laboratory, University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062843590","display_name":"Elias Kougianos","orcid":"https://orcid.org/0000-0002-1616-7628"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elias Kougianos","raw_affiliation_strings":["NanoSystem Design Laboratory, University of North Texas, Denton, TX, USA","NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"NanoSystem Design Laboratory, University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"NanoSystem Design Laboratory, University of North Texas, Denton, TX 76203, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5044487544"],"corresponding_institution_ids":["https://openalex.org/I123534392"],"apc_list":null,"apc_paid":null,"fwci":2.1197,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.8827652,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/metamodeling","display_name":"Metamodeling","score":0.8024232387542725},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.7599354386329651},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.6955929398536682},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6015437245368958},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5634989738464355},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5172496438026428},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.48303350806236267},{"id":"https://openalex.org/keywords/tabu-search","display_name":"Tabu search","score":0.45728370547294617},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.44869378209114075},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43450841307640076},{"id":"https://openalex.org/keywords/optimization-problem","display_name":"Optimization problem","score":0.4297780394554138},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4179037809371948},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37987926602363586},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3632490634918213},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28245240449905396},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22240212559700012},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20228955149650574},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07699435949325562}],"concepts":[{"id":"https://openalex.org/C86610423","wikidata":"https://www.wikidata.org/wiki/Q1925081","display_name":"Metamodeling","level":2,"score":0.8024232387542725},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.7599354386329651},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.6955929398536682},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6015437245368958},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5634989738464355},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5172496438026428},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.48303350806236267},{"id":"https://openalex.org/C123370116","wikidata":"https://www.wikidata.org/wiki/Q1424540","display_name":"Tabu search","level":2,"score":0.45728370547294617},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.44869378209114075},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43450841307640076},{"id":"https://openalex.org/C137836250","wikidata":"https://www.wikidata.org/wiki/Q984063","display_name":"Optimization problem","level":2,"score":0.4297780394554138},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4179037809371948},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37987926602363586},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3632490634918213},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28245240449905396},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22240212559700012},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20228955149650574},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07699435949325562},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770758","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W604599845","https://openalex.org/W1550644388","https://openalex.org/W1585651733","https://openalex.org/W1680603978","https://openalex.org/W2018352709","https://openalex.org/W2040604914","https://openalex.org/W2055261421","https://openalex.org/W2056760934","https://openalex.org/W2070334657","https://openalex.org/W2097268763","https://openalex.org/W2099528214","https://openalex.org/W2100215167","https://openalex.org/W2101197344","https://openalex.org/W2104369926","https://openalex.org/W2113068346","https://openalex.org/W2115721827","https://openalex.org/W2118236423","https://openalex.org/W2120036863","https://openalex.org/W2120040962","https://openalex.org/W2124927125","https://openalex.org/W2128566764","https://openalex.org/W2134753955","https://openalex.org/W2141776905","https://openalex.org/W2146679960","https://openalex.org/W2160564549","https://openalex.org/W2163881698","https://openalex.org/W2165666706","https://openalex.org/W2536704639","https://openalex.org/W3139715205","https://openalex.org/W3159171969","https://openalex.org/W4212875957","https://openalex.org/W4213283575","https://openalex.org/W4247388665","https://openalex.org/W4252303407"],"related_works":["https://openalex.org/W1557016741","https://openalex.org/W2098869417","https://openalex.org/W2170057471","https://openalex.org/W2106223679","https://openalex.org/W2106548485","https://openalex.org/W2171413119","https://openalex.org/W2503215586","https://openalex.org/W4298123071","https://openalex.org/W2042338187","https://openalex.org/W2295569708"],"abstract_inverted_index":{"Design":[0],"optimization":[1,25,48,57,94,148],"methodologies":[2],"for":[3,112,120,137],"AMS-SoCs":[4],"with":[5],"analog,":[6],"digital,":[7],"and":[8,26,83,102,126],"mixed-signal":[9,22],"portions":[10],"have":[11],"not":[12],"received":[13],"significant":[14],"attention,":[15],"due":[16],"to":[17,45,108],"their":[18,110],"high":[19],"complexity.":[20],"In":[21,89],"circuit":[23,70,76],"design,":[24],"simulation":[27],"are":[28,96,106],"still":[29],"important":[30],"issues":[31],"as":[32,133],"they":[33],"make":[34],"the":[35,54,69,74,85,127,145,154],"design":[36,47,80,86],"cycle":[37,87],"longer.":[38],"This":[39],"paper":[40,91],"presents":[41],"a":[42,61,121,134,138],"new":[43],"approach":[44,51],"reduce":[46,84],"time.":[49,88],"The":[50],"relies":[52],"on":[53],"fact":[55],"that":[56,144],"carried":[58],"out":[59],"over":[60,153],"metamodel":[62],"(which":[63],"is":[64,118,131,142],"an":[65],"abstracted":[66],"representation":[67],"of":[68,73],"model)":[71],"instead":[72],"actual":[75,155],"will":[77],"allow":[78],"fast":[79],"space":[81],"exploration":[82],"this":[90],"three":[92],"different":[93],"algorithms":[95,105],"compared:":[97],"exhaustive":[98],"search,":[99],"tabu":[100],"search":[101],"simulated":[103],"annealing":[104],"analyzed":[107],"determine":[109],"suitability":[111],"metamodeling-based":[113],"optimization.":[114,157],"A":[115],"ring":[116],"oscillator":[117],"designed":[119],"45":[122],"nm":[123],"nano-CMOS":[124],"technology":[125],"post-layout":[128],"parasitic":[129],"netlist":[130],"used":[132],"test":[135],"case":[136],"comparative":[139],"study.":[140],"It":[141],"observed":[143],"metamodel-based":[146],"simulated-annealing":[147],"algorithm":[149],"achieved":[150],"~9000\u00d7":[151],"speed-up":[152],"circuit-based":[156]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
