{"id":"https://openalex.org/W2118125642","doi":"https://doi.org/10.1109/isqed.2011.5770752","title":"Delay optimization considering power saving in dynamic CMOS circuits","display_name":"Delay optimization considering power saving in dynamic CMOS circuits","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2118125642","doi":"https://doi.org/10.1109/isqed.2011.5770752","mag":"2118125642"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074738133","display_name":"Kumar Yelamarthi","orcid":"https://orcid.org/0000-0002-0072-3909"},"institutions":[{"id":"https://openalex.org/I1629065","display_name":"Central Michigan University","ror":"https://ror.org/02xawj266","country_code":"US","type":"education","lineage":["https://openalex.org/I1629065"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kumar Yelamarthi","raw_affiliation_strings":["Central Michigan University, Mount Pleasant, MI, USA","Central Michigan University, Mt Pleasant, MI, USA"],"affiliations":[{"raw_affiliation_string":"Central Michigan University, Mount Pleasant, MI, USA","institution_ids":["https://openalex.org/I1629065"]},{"raw_affiliation_string":"Central Michigan University, Mt Pleasant, MI, USA","institution_ids":["https://openalex.org/I1629065"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064237316","display_name":"Chien\u2010In Henry Chen","orcid":"https://orcid.org/0000-0002-2304-7237"},"institutions":[{"id":"https://openalex.org/I19648265","display_name":"Wright State University","ror":"https://ror.org/04qk6pt94","country_code":"US","type":"education","lineage":["https://openalex.org/I19648265"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chien-In Henry Chen","raw_affiliation_strings":["Wright State University, Dayton, OH, USA","Wright State Univ., Dayton, OH, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Wright State University, Dayton, OH, USA","institution_ids":["https://openalex.org/I19648265"]},{"raw_affiliation_string":"Wright State Univ., Dayton, OH, USA#TAB#","institution_ids":["https://openalex.org/I19648265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074738133"],"corresponding_institution_ids":["https://openalex.org/I1629065"],"apc_list":null,"apc_paid":null,"fwci":0.265,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63140373,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7617829442024231},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7046597003936768},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6857203245162964},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.6242111921310425},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5817825794219971},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5788437128067017},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5642037391662598},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.5577366352081299},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5360273718833923},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.45704323053359985},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4536133110523224},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4449646770954132},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4396512508392334},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.40632978081703186},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.40151867270469666},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.20756447315216064},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2026510238647461},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18315905332565308},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16887661814689636},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1663648784160614}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7617829442024231},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7046597003936768},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6857203245162964},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.6242111921310425},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5817825794219971},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5788437128067017},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5642037391662598},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.5577366352081299},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5360273718833923},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.45704323053359985},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4536133110523224},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4449646770954132},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4396512508392334},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.40632978081703186},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.40151867270469666},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.20756447315216064},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2026510238647461},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18315905332565308},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16887661814689636},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1663648784160614},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8199999928474426,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W175606318","https://openalex.org/W1508076293","https://openalex.org/W1517661712","https://openalex.org/W1518236483","https://openalex.org/W1569550779","https://openalex.org/W1989859908","https://openalex.org/W2017962632","https://openalex.org/W2033443176","https://openalex.org/W2050886972","https://openalex.org/W2088115909","https://openalex.org/W2100115371","https://openalex.org/W2100661413","https://openalex.org/W2108790707","https://openalex.org/W2117648153","https://openalex.org/W2129523677","https://openalex.org/W2133877139","https://openalex.org/W2149661268","https://openalex.org/W2150547314","https://openalex.org/W2161203815","https://openalex.org/W6607056725","https://openalex.org/W6634336121","https://openalex.org/W6672852001","https://openalex.org/W6674622291"],"related_works":["https://openalex.org/W3015599398","https://openalex.org/W4225162125","https://openalex.org/W2188730438","https://openalex.org/W2792778858","https://openalex.org/W2157230896","https://openalex.org/W2034656493","https://openalex.org/W2362904186","https://openalex.org/W2981674658","https://openalex.org/W4213093630","https://openalex.org/W2142535542"],"abstract_inverted_index":{"Performance":[0],"variation":[1,15],"is":[2,16,40,43,65],"one":[3],"of":[4,45,71,81,88,93,107,130],"the":[5,69,76,79,100,105,110,131,143],"primary":[6],"concerns":[7],"in":[8,18,28,58,75,85,109,122,151],"nanometer-scale":[9],"dynamic":[10,59],"CMOS":[11,60,141],"circuits.":[12,61],"This":[13],"performance":[14],"worse":[17],"circuits":[19],"with":[20],"multiple":[21],"timing":[22,73],"paths":[23,74,89],"such":[24],"as":[25],"those":[26],"used":[27],"microprocessors.":[29],"In":[30,96],"this":[31,123],"paper,":[32],"a":[33,117],"Process":[34],"Variation-aware":[35],"Transistor":[36],"(PVT)":[37],"sizing":[38,136],"algorithm":[39,64,124,145],"proposed,":[41],"which":[42,113],"capable":[44],"significantly":[46],"reducing":[47,104],"worst-case":[48,152],"delay,":[49],"delay":[50,53,153,156,160],"uncertainty,":[51],"and":[52,134,164],"sensitivity":[54,161],"to":[55,90,116,170],"process":[56],"variations":[57],"The":[62],"proposed":[63,144],"based":[66],"on":[67],"identifying":[68],"significance":[70],"all":[72],"design,":[77],"increasing":[78],"sizes":[80],"transistors":[82,108],"that":[83],"appear":[84],"most":[86,94],"number":[87],"reduce":[91],"delays":[92],"paths.":[95],"parallel,":[97],"it":[98],"minimizes":[99],"channel":[101],"load":[102],"by":[103,154,158,162,166],"size":[106],"interacting":[111],"paths,":[112],"will":[114],"lead":[115],"power":[118],"saving.":[119],"Additional":[120],"advantages":[121],"include":[125],"its":[126],"simplicity,":[127],"accuracy,":[128],"independent":[129],"transistor":[132],"order,":[133],"initial":[135,172],"factors.":[137],"Using":[138],"90":[139],"nm":[140],"process,":[142],"has":[146],"demonstrated":[147],"an":[148],"average":[149],"improvement":[150],"36.9%,":[155],"uncertainty":[157],"44.1%,":[159],"19.8%,":[163],"power-delay-product":[165],"35.3%":[167],"when":[168],"compared":[169],"their":[171],"performances.":[173]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
