{"id":"https://openalex.org/W1980005486","doi":"https://doi.org/10.1109/isqed.2011.5770730","title":"An automated design methodology for yield aware analog circuit synthesis in submicron technology","display_name":"An automated design methodology for yield aware analog circuit synthesis in submicron technology","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W1980005486","doi":"https://doi.org/10.1109/isqed.2011.5770730","mag":"1980005486"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770730","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770730","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044863803","display_name":"Sabyasachi Deyati","orcid":"https://orcid.org/0000-0001-9172-2495"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sabyasachi Deyati","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, India","[Indian Inst. of Technol., Kharagpur]"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"[Indian Inst. of Technol., Kharagpur]","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109378297","display_name":"Pradip Mandal","orcid":"https://orcid.org/0000-0002-3767-7299"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pradip Mandal","raw_affiliation_strings":["Indian Institute of Technology Kharagpur, India","[Indian Inst. of Technol., Kharagpur]"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"[Indian Inst. of Technol., Kharagpur]","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5044863803"],"corresponding_institution_ids":["https://openalex.org/I145894827"],"apc_list":null,"apc_paid":null,"fwci":1.5897,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.84061078,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6086685657501221},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.6062523722648621},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5802001357078552},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5494288206100464},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.5412663221359253},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.5066891312599182},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5054366588592529},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.5035175681114197},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5028254389762878},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4881599545478821},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.47043320536613464},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46681925654411316},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4460000693798065},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.44386667013168335},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.4339711666107178},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.4239824414253235},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.37188172340393066},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2681666314601898},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24950510263442993},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.21309539675712585},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21086660027503967},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18322327733039856},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10212108492851257},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09319612383842468}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6086685657501221},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.6062523722648621},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5802001357078552},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5494288206100464},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.5412663221359253},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.5066891312599182},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5054366588592529},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.5035175681114197},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5028254389762878},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4881599545478821},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.47043320536613464},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46681925654411316},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4460000693798065},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.44386667013168335},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.4339711666107178},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.4239824414253235},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.37188172340393066},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2681666314601898},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24950510263442993},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.21309539675712585},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21086660027503967},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18322327733039856},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10212108492851257},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09319612383842468},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770730","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770730","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2078592402","https://openalex.org/W2106476087","https://openalex.org/W2115721827","https://openalex.org/W2122919983","https://openalex.org/W2136938727","https://openalex.org/W2161299762","https://openalex.org/W2294458522","https://openalex.org/W3139715205","https://openalex.org/W4249003824","https://openalex.org/W4250888461","https://openalex.org/W6684057376","https://openalex.org/W6686215914","https://openalex.org/W6830100082"],"related_works":["https://openalex.org/W3080940989","https://openalex.org/W4287685600","https://openalex.org/W2091329789","https://openalex.org/W2304374807","https://openalex.org/W2967850598","https://openalex.org/W2376028644","https://openalex.org/W2583707817","https://openalex.org/W4292182797","https://openalex.org/W2253173388","https://openalex.org/W1964352816"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,106],"new":[4],"fully":[5],"automated":[6],"design":[7,63,72,79,86,109,143,179],"methodology":[8],"for":[9,162],"analog":[10],"circuit":[11,18,22,53],"synthesis":[12],"in":[13,117,127,178],"submicron":[14,43],"technology.":[15],"It":[16],"requires":[17],"topology":[19],"and":[20,26,88,152,181],"desired":[21],"performance":[23],"as":[24],"input":[25],"it":[27],"produces":[28],"not":[29,94],"only":[30],"the":[31,36,39,61,67,70,78,84,91,142],"sized":[32,40],"netlist":[33],"but":[34,134],"also":[35],"layout":[37,161,173,189],"of":[38,69,90],"components.":[41],"Today's":[42],"technology":[44,146],"accompanies":[45],"appreciable":[46],"process":[47,76,155],"variation.":[48],"In":[49],"conventional":[50],"equation":[51],"based":[52],"sizing":[54],"technique":[55,111],"there":[56],"is":[57,65,103,132,190],"high":[58],"chance":[59],"that":[60],"optimized":[62],"point":[64,80],"at":[66],"boundary":[68],"feasible":[71,85],"space.":[73],"Due":[74],"to":[75,104,112,123,140,145,153],"variation":[77,156],"may":[81],"fall":[82],"outside":[83],"space":[87],"some":[89,163],"specifications":[92],"are":[93,121,176,194],"meet":[95],"after":[96],"fabrication,":[97],"resulting":[98],"poor":[99],"yield.":[100],"Our":[101],"intention":[102],"formulate":[105],"computationally":[107],"inexpensive":[108],"centering":[110],"circumvent":[113],"this":[114],"yield":[115],"problem":[116],"design.":[118],"Analog":[119],"designs":[120],"sensitive":[122],"its":[124],"layout.":[125],"Though":[126],"simulation":[128],"any":[129],"device":[130,184],"dimension":[131,185],"possible":[133],"while":[135],"doing":[136],"layout,":[137],"designers":[138,157],"need":[139],"bring":[141],"conforming":[144],"grid":[147],"point.":[148],"For":[149],"better":[150],"matching":[151],"reduce":[154],"do":[158],"common":[159],"centroid":[160],"special":[164],"transistor":[165,170],"pairs":[166],"(differential":[167],"pair,":[168],"mirroring":[169],"etc.).":[171],"Those":[172],"related":[174],"issues":[175],"considered":[177],"phase":[180],"we":[182],"produce":[183],"with":[186],"which":[187],"direct":[188],"possible.":[191],"Layout":[192],"components":[193],"generated":[195],"automatically":[196],"through":[197],"pcell":[198],"by":[199],"cadence":[200],"SKILL.":[201]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
