{"id":"https://openalex.org/W2133590277","doi":"https://doi.org/10.1109/isqed.2011.5770724","title":"A complete framework of simultaneous functional unit and register binding with skew scheduling","display_name":"A complete framework of simultaneous functional unit and register binding with skew scheduling","publication_year":2011,"publication_date":"2011-03-01","ids":{"openalex":"https://openalex.org/W2133590277","doi":"https://doi.org/10.1109/isqed.2011.5770724","mag":"2133590277"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2011.5770724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112420841","display_name":"Mineo Kaneko","orcid":null},"institutions":[{"id":"https://openalex.org/I177738480","display_name":"Japan Advanced Institute of Science and Technology","ror":"https://ror.org/03frj4r98","country_code":"JP","type":"education","lineage":["https://openalex.org/I177738480"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Mineo Kaneko","raw_affiliation_strings":["School of Information Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, Japan","School of Information Science, Japan Advanced Institute of Science and Technology, Nomi-shi, Ishikawa 923-1292, Japan"],"affiliations":[{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa, Japan","institution_ids":["https://openalex.org/I177738480"]},{"raw_affiliation_string":"School of Information Science, Japan Advanced Institute of Science and Technology, Nomi-shi, Ishikawa 923-1292, Japan","institution_ids":["https://openalex.org/I177738480"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5112420841"],"corresponding_institution_ids":["https://openalex.org/I177738480"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15412125,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9467179775238037},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7360216379165649},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7308462858200073},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7270935773849487},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.7172091603279114},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.6268619298934937},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.6196744441986084},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5950178503990173},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.5476819276809692},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5354037284851074},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4846935570240021},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.43556129932403564},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4053988456726074},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3195417821407318},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.31882143020629883},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25081923604011536},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.2003365159034729},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1656508445739746},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.15766742825508118},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11051958799362183},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.09945628046989441},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.09544673562049866},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.07449591159820557}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9467179775238037},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7360216379165649},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7308462858200073},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7270935773849487},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.7172091603279114},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6268619298934937},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.6196744441986084},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5950178503990173},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.5476819276809692},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5354037284851074},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4846935570240021},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.43556129932403564},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4053988456726074},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3195417821407318},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.31882143020629883},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25081923604011536},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2003365159034729},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1656508445739746},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.15766742825508118},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11051958799362183},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09945628046989441},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.09544673562049866},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.07449591159820557},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2011.5770724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2011.5770724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 12th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1511469799","https://openalex.org/W2000655923","https://openalex.org/W2011778848","https://openalex.org/W2093660707","https://openalex.org/W2111971510","https://openalex.org/W2138548848","https://openalex.org/W2138706204","https://openalex.org/W2150660745","https://openalex.org/W2164070656","https://openalex.org/W4255150597","https://openalex.org/W6650546730","https://openalex.org/W6684404753"],"related_works":["https://openalex.org/W4247089581","https://openalex.org/W4230501858","https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W1564063853","https://openalex.org/W2083529740","https://openalex.org/W2144282137","https://openalex.org/W2090556728","https://openalex.org/W2110292056","https://openalex.org/W2117863281"],"abstract_inverted_index":{"Intentional":[0],"skew":[1,24,45,94],"is":[2,59,66],"known":[3],"to":[4,13,70],"be":[5],"useful":[6],"for":[7,22,61],"improving":[8],"clock":[9],"frequency":[10],"and/or":[11],"tolerance":[12],"delay":[14],"variations.":[15],"This":[16],"paper":[17],"proposes":[18],"a":[19,62,76],"complete":[20,77],"framework":[21],"treating":[23],"schedule":[25],"in":[26],"the":[27,36,44,99,102],"high":[28],"level":[29],"datapath":[30,63],"synthesis.":[31],"Major":[32],"contributions":[33],"include":[34],"(1)":[35],"incorporation":[37],"of":[38,84,104],"timing":[39,50],"issue":[40,51],"on":[41,52],"multiplexer-control":[42],"into":[43],"scheduling":[46],"problem":[47],"(previously,":[48],"only":[49],"register-control":[53],"has":[54],"been":[55],"discussed,":[56],"but":[57],"it":[58],"incomplete":[60],"circuit":[64],"which":[65],"controlled":[67],"by":[68],"control-signals":[69],"registers":[71],"and":[72,74,90,101],"multiplexers),":[73],"(2)":[75],"MILP":[78],"(Mixed":[79],"Integer":[80],"Linear":[81],"Programming)":[82],"formulation":[83],"simultaneous":[85],"functional":[86],"unit":[87],"(FU)":[88],"binding":[89],"register":[91],"incorporating":[92],"with":[93],"scheduling.":[95],"Experimental":[96],"examples":[97],"demonstrate":[98],"correctness":[100],"effectiveness":[103],"our":[105],"framework.":[106]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
