{"id":"https://openalex.org/W2019487421","doi":"https://doi.org/10.1109/isqed.2010.5450531","title":"Body bias driven design synthesis for optimum performance per area","display_name":"Body bias driven design synthesis for optimum performance per area","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W2019487421","doi":"https://doi.org/10.1109/isqed.2010.5450531","mag":"2019487421"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2010.5450531","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450531","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research.tue.nl/en/publications/d9465457-c608-4d00-aa30-8cc27f59343a","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061465128","display_name":"Maurice Meijer","orcid":null},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"Maurice Meijer","raw_affiliation_strings":["NXP Semiconductors, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050945839","display_name":"Jos\u00e9 Pineda de Gyvez","orcid":"https://orcid.org/0000-0002-0723-7065"},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]},{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Jose Pineda de Gyvez","raw_affiliation_strings":["NXP Semiconductors, Eindhoven, Netherlands","Technical University Eindhoven, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I109147379"]},{"raw_affiliation_string":"Technical University Eindhoven, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5061465128"],"corresponding_institution_ids":["https://openalex.org/I109147379"],"apc_list":null,"apc_paid":null,"fwci":2.0205,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.87129207,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"472","last_page":"477"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5533850789070129}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5533850789070129}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/isqed.2010.5450531","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450531","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire/d9465457-c608-4d00-aa30-8cc27f59343a","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/d9465457-c608-4d00-aa30-8cc27f59343a","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Meijer, M & Pineda de Gyvez, J 2010, Body bias driven design synthesis for optimum performance per area. in Proceedings of the 2010 11th International Symposium on Quality Electronic Design (ISQED), 22-24 March 2010, San Jose, California. Institute of Electrical and Electronics Engineers, Piscataway, pp. 472-477. https://doi.org/10.1109/ISQED.2010.5450531","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:tue:oai:pure.tue.nl:publications/d9465457-c608-4d00-aa30-8cc27f59343a","is_oa":true,"landing_page_url":"https://research.tue.nl/nl/publications/d9465457-c608-4d00-aa30-8cc27f59343a","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the 2010 11th International Symposium on Quality Electronic Design (ISQED), 22-24 March 2010, San Jose, California, 472 - 477","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":{"id":"pmh:oai:pure.tue.nl:openaire/d9465457-c608-4d00-aa30-8cc27f59343a","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/d9465457-c608-4d00-aa30-8cc27f59343a","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Meijer, M & Pineda de Gyvez, J 2010, Body bias driven design synthesis for optimum performance per area. in Proceedings of the 2010 11th International Symposium on Quality Electronic Design (ISQED), 22-24 March 2010, San Jose, California. Institute of Electrical and Electronics Engineers, Piscataway, pp. 472-477. https://doi.org/10.1109/ISQED.2010.5450531","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1554898868","https://openalex.org/W2035925997","https://openalex.org/W2046737467","https://openalex.org/W2097466426","https://openalex.org/W2098736822","https://openalex.org/W2105545647","https://openalex.org/W2115435370","https://openalex.org/W2120527248","https://openalex.org/W2146743175","https://openalex.org/W2150526221","https://openalex.org/W2150713987","https://openalex.org/W3142888977","https://openalex.org/W3152061493","https://openalex.org/W4240067961","https://openalex.org/W4242819225","https://openalex.org/W4245614799","https://openalex.org/W6659183437","https://openalex.org/W6662041258","https://openalex.org/W6681979597"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2093578348","https://openalex.org/W2376932109","https://openalex.org/W2382290278","https://openalex.org/W2766271392","https://openalex.org/W2350741829","https://openalex.org/W3004735627"],"abstract_inverted_index":{"Worst-case":[0],"design":[1,24],"uses":[2],"extreme":[3],"process":[4],"corner":[5],"conditions":[6],"which":[7],"rarely":[8],"occur.":[9],"This":[10],"costs":[11],"additional":[12],"power":[13,54,94],"due":[14],"to":[15,63,83,90,98],"area":[16,85],"over-dimensioning":[17,48],"during":[18],"synthesis.":[19],"We":[20],"present":[21],"a":[22,41,69],"new":[23],"strategy":[25],"for":[26],"digital":[27],"CMOS":[28],"IP":[29],"that":[30],"makes":[31],"use":[32],"of":[33,61,71,96],"forward":[34],"body":[35],"biasing.":[36],"Our":[37],"approach":[38],"renders":[39],"consistently":[40],"better":[42],"performance-per-area":[43,80],"ratio":[44,60],"by":[45],"constraining":[46],"circuit":[47,51],"without":[49,100],"sacrificing":[50],"performance.":[52],"Dynamic":[53],"is":[55],"reduced":[56],"depending":[57],"upon":[58],"the":[59],"flip-flops":[62],"logic-gates,":[64],"and":[65,86,92],"data":[66],"activity.":[67],"On":[68],"set":[70],"benchmark":[72],"circuits":[73],"in":[74],"65":[75],"nm":[76],"LP-CMOS,":[77],"we":[78],"observed":[79],"improvements":[81],"up":[82,89,97],"81%,":[84],"leakage":[87],"reductions":[88],"38%,":[91],"total":[93],"savings":[95],"26%":[99],"performance":[101],"penalties.":[102]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}