{"id":"https://openalex.org/W2079653380","doi":"https://doi.org/10.1109/isqed.2010.5450526","title":"Synthesis and formal verification of on-chip protocol transducers through decomposed specification","display_name":"Synthesis and formal verification of on-chip protocol transducers through decomposed specification","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W2079653380","doi":"https://doi.org/10.1109/isqed.2010.5450526","mag":"2079653380"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2010.5450526","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450526","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I4210086780","display_name":"Japan Science and Technology Agency","ror":"https://ror.org/00097mb19","country_code":"JP","type":"government","lineage":["https://openalex.org/I1319490839","https://openalex.org/I4210086780"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["CREST, Japan Science and Technology Agency, Japan","VLSI Design and Education Center (VDEC), University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CREST, Japan Science and Technology Agency, Japan","institution_ids":["https://openalex.org/I4210086780"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063626632","display_name":"Hideo Tanida","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hideo Tanida","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001383535","display_name":"Fei Gao","orcid":"https://orcid.org/0000-0002-4678-1936"},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Fei Gao","raw_affiliation_strings":["Fujitsu Laboratories Limited, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories Limited, Japan","institution_ids":["https://openalex.org/I2252096349"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025475799","display_name":"Tasuku Nishihara","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tasuku Nishihara","raw_affiliation_strings":["Department of Electronic Engineering, University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054079223","display_name":"Takeshi Matsumoto","orcid":"https://orcid.org/0000-0002-1517-0761"},"institutions":[{"id":"https://openalex.org/I4210086780","display_name":"Japan Science and Technology Agency","ror":"https://ror.org/00097mb19","country_code":"JP","type":"government","lineage":["https://openalex.org/I1319490839","https://openalex.org/I4210086780"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takeshi Matsumoto","raw_affiliation_strings":["CREST, Japan Science and Technology Agency, Japan","VLSI Design and Education Center (VDEC), University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CREST, Japan Science and Technology Agency, Japan","institution_ids":["https://openalex.org/I4210086780"]},{"raw_affiliation_string":"VLSI Design and Education Center (VDEC), University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"515","last_page":"523"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9022191762924194},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.8004117012023926},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7945215702056885},{"id":"https://openalex.org/keywords/transducer","display_name":"Transducer","score":0.6952014565467834},{"id":"https://openalex.org/keywords/communications-protocol","display_name":"Communications protocol","score":0.5089662075042725},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.49443936347961426},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.46212315559387207},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.4252786338329315},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42007583379745483},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22413983941078186},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15995579957962036},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15906721353530884},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10310453176498413},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07336220145225525}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9022191762924194},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.8004117012023926},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7945215702056885},{"id":"https://openalex.org/C56318395","wikidata":"https://www.wikidata.org/wiki/Q215928","display_name":"Transducer","level":2,"score":0.6952014565467834},{"id":"https://openalex.org/C12269588","wikidata":"https://www.wikidata.org/wiki/Q132364","display_name":"Communications protocol","level":2,"score":0.5089662075042725},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.49443936347961426},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.46212315559387207},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.4252786338329315},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42007583379745483},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22413983941078186},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15995579957962036},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15906721353530884},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10310453176498413},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07336220145225525},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2010.5450526","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450526","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2004157466","https://openalex.org/W2047314385","https://openalex.org/W2152864604","https://openalex.org/W2402898942","https://openalex.org/W3148564761","https://openalex.org/W4285719527","https://openalex.org/W6651476532","https://openalex.org/W6713318838"],"related_works":["https://openalex.org/W2152752131","https://openalex.org/W161255303","https://openalex.org/W1544097700","https://openalex.org/W1488573418","https://openalex.org/W1922520186","https://openalex.org/W1946493810","https://openalex.org/W2391979747","https://openalex.org/W2981877881","https://openalex.org/W2550448639","https://openalex.org/W1964135497"],"abstract_inverted_index":{"Protocol":[0],"transducer":[1,101],"which":[2,53,111],"realizes":[3],"translations":[4],"between":[5,97],"multiple":[6],"protocols":[7,59],"is":[8],"one":[9],"of":[10,26,67,76,82,129],"the":[11,41,68,79,83,98,106,130],"key":[12],"components":[13],"in":[14,40,78],"IP-based":[15],"design":[16,132],"methodology.":[17],"Although":[18],"there":[19],"have":[20],"been":[21],"researches":[22],"on":[23,94],"automatic":[24,50],"synthesis":[25,51,117],"such":[27],"protocol":[28,70,84,100,109,139,155],"transducers,":[29],"they":[30],"cannot":[31],"efficiently":[32,143],"deal":[33,55],"with":[34,56],"out-of-order":[35],"type":[36],"communications":[37],"frequently":[38],"found":[39],"state-of-the-art":[42,58,159],"protocols.":[43,160],"In":[44],"this":[45],"paper":[46],"we":[47],"present":[48,88],"an":[49],"method":[52,92],"can":[54,112,141],"complicated":[57,138,158],"by":[60,125],"clearly":[61],"separating":[62],"control":[63],"and":[64,72,105,133,137,144],"datapath":[65,80],"parts":[66,81],"synthesized":[69],"transducers":[71,110,140,156],"introducing":[73],"four":[74],"types":[75],"configurations":[77],"transducers.":[85],"We":[86],"also":[87],"a":[89,126],"formal":[90],"verification":[91],"based":[93],"inclusion":[95],"checking":[96],"given":[99],"to":[102],"be":[103,113,142],"verified":[104],"all":[107],"possible":[108],"generated":[114],"through":[115],"our":[116],"method.":[118],"By":[119],"using":[120],"simulation-based":[121],"filtering":[122],"methods":[123],"followed":[124],"complete":[127],"analysis":[128],"entire":[131],"state":[134],"space,":[135],"large":[136],"formally":[145],"verified.":[146],"Experimental":[147],"results":[148],"show":[149],"their":[150],"practical":[151],"usefulness":[152],"even":[153],"for":[154,157]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}