{"id":"https://openalex.org/W2023826858","doi":"https://doi.org/10.1109/isqed.2010.5450451","title":"Structural fault collapsing by superposition of BDDs for test generation in digital circuits","display_name":"Structural fault collapsing by superposition of BDDs for test generation in digital circuits","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W2023826858","doi":"https://doi.org/10.1109/isqed.2010.5450451","mag":"2023826858"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2010.5450451","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450451","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010536057","display_name":"Raimund Ubar","orcid":"https://orcid.org/0000-0001-8186-4385"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"R. Ubar","raw_affiliation_strings":["Department of Computer Engineering, TTU, Tallinn, Estonia","Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, TTU, Tallinn, Estonia","institution_ids":[]},{"raw_affiliation_string":"Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065669857","display_name":"Dmitri Mironov","orcid":"https://orcid.org/0009-0008-7223-1939"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"D. Mironov","raw_affiliation_strings":["Department of Computer Engineering, TTU, Tallinn, Estonia","Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, TTU, Tallinn, Estonia","institution_ids":[]},{"raw_affiliation_string":"Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010286547","display_name":"Jaan Raik","orcid":"https://orcid.org/0000-0001-8113-020X"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"J. Raik","raw_affiliation_strings":["Department of Computer Engineering, TTU, Tallinn, Estonia","Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, TTU, Tallinn, Estonia","institution_ids":[]},{"raw_affiliation_string":"Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059021602","display_name":"Artur Jutman","orcid":"https://orcid.org/0000-0002-2018-5589"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"A. Jutman","raw_affiliation_strings":["Department of Computer Engineering, TTU, Tallinn, Estonia","Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, TTU, Tallinn, Estonia","institution_ids":[]},{"raw_affiliation_string":"Department of Computer Engineering, TTU, Ehitajate tee 5, 19086 Tallinn, Estonia","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5010536057"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":1.7527,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.85309405,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"16","issue":null,"first_page":"250","last_page":"257"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/binary-decision-diagram","display_name":"Binary decision diagram","score":0.7340821027755737},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6553084254264832},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.6350188851356506},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5800732970237732},{"id":"https://openalex.org/keywords/superposition-principle","display_name":"Superposition principle","score":0.5588464140892029},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5580704212188721},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5487219095230103},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.509615421295166},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.5041972398757935},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.46112746000289917},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.38379716873168945},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.32676178216934204},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.25568726658821106},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2510598301887512},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19774234294891357}],"concepts":[{"id":"https://openalex.org/C3309909","wikidata":"https://www.wikidata.org/wiki/Q864155","display_name":"Binary decision diagram","level":2,"score":0.7340821027755737},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6553084254264832},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.6350188851356506},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5800732970237732},{"id":"https://openalex.org/C27753989","wikidata":"https://www.wikidata.org/wiki/Q284885","display_name":"Superposition principle","level":2,"score":0.5588464140892029},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5580704212188721},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5487219095230103},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.509615421295166},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.5041972398757935},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.46112746000289917},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.38379716873168945},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.32676178216934204},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.25568726658821106},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2510598301887512},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19774234294891357},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2010.5450451","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450451","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1539901529","https://openalex.org/W1964866107","https://openalex.org/W1994143452","https://openalex.org/W2010935983","https://openalex.org/W2017500854","https://openalex.org/W2080267935","https://openalex.org/W2099251677","https://openalex.org/W2108159261","https://openalex.org/W2109508018","https://openalex.org/W2110413274","https://openalex.org/W2111525550","https://openalex.org/W2112078647","https://openalex.org/W2118354996","https://openalex.org/W2118815983","https://openalex.org/W2140558640","https://openalex.org/W2142900162","https://openalex.org/W2148757937","https://openalex.org/W2152040677","https://openalex.org/W2156524662","https://openalex.org/W2159880265","https://openalex.org/W2546264495","https://openalex.org/W3144300655","https://openalex.org/W4230587734","https://openalex.org/W4254777046","https://openalex.org/W6652961831"],"related_works":["https://openalex.org/W2340957901","https://openalex.org/W4256030018","https://openalex.org/W2147400189","https://openalex.org/W3147038789","https://openalex.org/W2068571131","https://openalex.org/W1555400249","https://openalex.org/W2092357065","https://openalex.org/W2115005577","https://openalex.org/W2913077774","https://openalex.org/W2952274626"],"abstract_inverted_index":{"The":[0,22,37,135],"paper":[1],"presents":[2],"a":[3,61,69,75,87],"new":[4,70],"structural":[5,127],"fault-independent":[6],"fault":[7,43,67,101,115,128],"collapsing":[8,44,116,129],"method":[9,120,136],"based":[10],"on":[11],"the":[12,16,29,47,66,91,107,114,118],"topology":[13],"analysis":[14],"of":[15,26,49,72,77,90,145],"circuit,":[17],"which":[18,85],"has":[19],"linear":[20],"complexity.":[21],"minimal":[23],"necessary":[24],"set":[25],"faults":[27],"as":[28,60],"target":[30],"objective":[31],"for":[32,57,94,140],"test":[33,58,95],"generation":[34,96],"is":[35,40,83,121,137],"found.":[36],"main":[38],"idea":[39],"to":[41],"produce":[42],"concurrently":[45],"with":[46,79,103,131,142],"construction":[48],"structurally":[50],"synthesized":[51],"binary":[52],"decision":[53],"diagrams":[54],"(SSBDD)":[55],"used":[56],"generation,":[59],"side":[62],"effect.":[63],"To":[64],"improve":[65],"collapsing,":[68],"class":[71],"BDDs":[73],"in":[74],"form":[76],"SSBDDs":[78,108],"multiple":[80],"inputs":[81],"(SSMIBDD)":[82],"proposed,":[84],"allows":[86],"significant":[88],"reduction":[89],"model":[92],"complexity":[93],"purposes,":[97],"and":[98],"produces":[99],"collapsed":[100],"sets":[102],"less":[104],"sizes":[105],"than":[106,125],"provide.":[109],"Experimental":[110],"data":[111],"show":[112],"that":[113],"by":[117],"proposed":[119],"considerably":[122],"more":[123],"efficient":[124,139],"other":[126],"methods":[130],"comparative":[132],"time":[133],"cost.":[134],"especially":[138],"circuits":[141],"high":[143],"rate":[144],"internal":[146],"fanouts.":[147]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
