{"id":"https://openalex.org/W2123047626","doi":"https://doi.org/10.1109/isqed.2010.5450415","title":"A framework for logic-aware layout analysis","display_name":"A framework for logic-aware layout analysis","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W2123047626","doi":"https://doi.org/10.1109/isqed.2010.5450415","mag":"2123047626"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2010.5450415","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450415","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053770718","display_name":"P. J. Gibson","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":true,"raw_author_name":"Patrick Gibson","raw_affiliation_strings":["Mentor Graphics Corporation, Hungary","Mentor Graphics Corporation USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Hungary","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Mentor Graphics Corporation USA","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011895602","display_name":"Ziyang Lu","orcid":"https://orcid.org/0000-0003-2050-5180"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Ziyang Lu","raw_affiliation_strings":["Mentor Graphics Corporation, Hungary","Mentor Graphics Corporation USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Hungary","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Mentor Graphics Corporation USA","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061711514","display_name":"Fedor G. Pikus","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Fedor Pikus","raw_affiliation_strings":["Mentor Graphics Corporation, Hungary","Mentor Graphics Corporation USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Hungary","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Mentor Graphics Corporation USA","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114016043","display_name":"Sridhar Srinivasan","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Sridhar Srinivasan","raw_affiliation_strings":["Mentor Graphics Corporation, Hungary","Mentor Graphics Corporation USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, Hungary","institution_ids":["https://openalex.org/I105695857"]},{"raw_affiliation_string":"Mentor Graphics Corporation USA","institution_ids":["https://openalex.org/I105695857"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5053770718"],"corresponding_institution_ids":["https://openalex.org/I105695857"],"apc_list":null,"apc_paid":null,"fwci":0.4994,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.68063988,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"171","last_page":"175"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7445571422576904},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.7160944938659668},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5895305871963501},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5560191869735718},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5408592224121094},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5306752324104309},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.4754481017589569},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45689675211906433},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.43688058853149414},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4307405352592468},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4286133646965027},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.33455994725227356},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.17868685722351074},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14520755410194397},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14460521936416626},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08434471487998962},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07756739854812622}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7445571422576904},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.7160944938659668},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5895305871963501},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5560191869735718},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5408592224121094},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5306752324104309},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.4754481017589569},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45689675211906433},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.43688058853149414},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4307405352592468},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4286133646965027},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.33455994725227356},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.17868685722351074},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14520755410194397},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14460521936416626},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08434471487998962},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07756739854812622},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2010.5450415","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450415","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1989891105","https://openalex.org/W1994159986","https://openalex.org/W2076094440","https://openalex.org/W2114105164","https://openalex.org/W4242562544","https://openalex.org/W6648022024","https://openalex.org/W6824975774"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W1553855433","https://openalex.org/W1488117239","https://openalex.org/W2082788688","https://openalex.org/W2146588118","https://openalex.org/W3129977055","https://openalex.org/W1792381030","https://openalex.org/W2304188393","https://openalex.org/W2130825721","https://openalex.org/W2077400643"],"abstract_inverted_index":{"In":[0],"this":[1,48],"paper,":[2],"we":[3,52],"explain":[4],"a":[5],"new":[6,49],"EDA":[7],"tool":[8],"framework":[9,50],"that":[10],"extends":[11],"the":[12,23,33,39,42,45,62,66,69,76],"reach":[13],"of":[14,32,44,57,65],"Electrical":[15],"DFM":[16],"analysis":[17,28,31,64,71],"across":[18],"cross-domain":[19],"applications":[20,56],"by":[21,74],"providing":[22],"ability":[24],"to":[25],"do":[26],"layout":[27,58],"and":[29,41],"logical":[30],"schematics":[34],"in":[35],"context.":[36],"To":[37],"demonstrate":[38],"effectiveness":[40],"flexibility":[43],"integrated":[46],"environment":[47],"provides,":[51],"show":[53],"several":[54],"real-time":[55],"verification":[59],"based":[60],"on":[61],"logic":[63,70],"circuit,":[67],"where":[68],"is":[72],"performed":[73],"applying":[75],"correct":[77],"design":[78],"rules.":[79]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}