{"id":"https://openalex.org/W2149402992","doi":"https://doi.org/10.1109/isqed.2010.5450398","title":"Clock buffer polarity assignment considering the effect of delay variations","display_name":"Clock buffer polarity assignment considering the effect of delay variations","publication_year":2010,"publication_date":"2010-03-01","ids":{"openalex":"https://openalex.org/W2149402992","doi":"https://doi.org/10.1109/isqed.2010.5450398","mag":"2149402992"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2010.5450398","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080626961","display_name":"Minseok Kang","orcid":"https://orcid.org/0000-0002-2397-9691"},"institutions":[{"id":"https://openalex.org/I118373667","display_name":"Seoul National University of Science and Technology","ror":"https://ror.org/00chfja07","country_code":"KR","type":"education","lineage":["https://openalex.org/I118373667"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Minseok Kang","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Seoul National University of Technology, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Seoul National University of Technology, South Korea","institution_ids":["https://openalex.org/I118373667"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049474875","display_name":"Taewhan Kim","orcid":"https://orcid.org/0000-0002-6114-3772"},"institutions":[{"id":"https://openalex.org/I118373667","display_name":"Seoul National University of Science and Technology","ror":"https://ror.org/00chfja07","country_code":"KR","type":"education","lineage":["https://openalex.org/I118373667"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taewhan Kim","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Seoul National University of Technology, South Korea"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Seoul National University of Technology, South Korea","institution_ids":["https://openalex.org/I118373667"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5080626961"],"corresponding_institution_ids":["https://openalex.org/I118373667"],"apc_list":null,"apc_paid":null,"fwci":1.1546,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.81801066,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"69","last_page":"74"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.7157201766967773},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7055110335350037},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5290718674659729},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.44088014960289},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22083482146263123},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1126563549041748},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07026919722557068}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.7157201766967773},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7055110335350037},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5290718674659729},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.44088014960289},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22083482146263123},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1126563549041748},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07026919722557068},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2010.5450398","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2010.5450398","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1572287951","https://openalex.org/W1792392580","https://openalex.org/W1988123824","https://openalex.org/W2018386086","https://openalex.org/W2023981464","https://openalex.org/W2044620840","https://openalex.org/W2079770493","https://openalex.org/W2101929352","https://openalex.org/W2102627413","https://openalex.org/W2108050730","https://openalex.org/W2121274710","https://openalex.org/W2122944491","https://openalex.org/W2136328167","https://openalex.org/W2163262735","https://openalex.org/W2165478440","https://openalex.org/W2170428543","https://openalex.org/W2476075474","https://openalex.org/W2620102549","https://openalex.org/W2964161462","https://openalex.org/W3150625878","https://openalex.org/W4229745658","https://openalex.org/W4238752581","https://openalex.org/W4248944487","https://openalex.org/W6637950021","https://openalex.org/W6641884055","https://openalex.org/W6670524841","https://openalex.org/W6680337182"],"related_works":["https://openalex.org/W2164834710","https://openalex.org/W4232019485","https://openalex.org/W2028052815","https://openalex.org/W4327499872","https://openalex.org/W2123512677","https://openalex.org/W2163318442","https://openalex.org/W2116259070","https://openalex.org/W2128528443","https://openalex.org/W2066822161","https://openalex.org/W2132548233"],"abstract_inverted_index":{"This":[0],"work":[1],"addresses":[2],"the":[3,16,20,25,31,34,58,67,71,82,90,106,113,122,144,150,156,174,179,188,224,227,236],"problem":[4,91,123],"of":[5,27,45,53,60,63,92,134,138,141],"minimizing":[6],"power/ground":[7,107,189],"noise":[8,108],"with":[9,77,193,214],"an":[10],"important":[11],"design":[12],"parameter,":[13],"which":[14,48,232],"is":[15,109,160,170,198,204],"delay":[17,28,59,69,79,237],"variations":[18,29],"on":[19,30,57,211],"clock":[21,37,72,83,116,157],"tree.":[22],"Without":[23],"considering":[24],"effect":[26],"polarity":[32,94,229],"assignment,":[33],"resulting":[35],"statistical":[36],"skew":[38,46,84,117,158],"may":[39],"lead":[40],"to":[41,74,95,143,172,176,186,206],"a":[42,50,101,136,166],"high":[43],"probability":[44],"violation,":[47],"causes":[49],"low":[51],"yield":[52,86,114,151,208],"design.":[54],"Given":[55],"distributions":[56],"each":[61,96,132],"type":[62],"buffering":[64,102],"elements":[65],"and":[66,81,85,115,162,218],"interconnect":[68],"from":[70,178],"source":[73],"every":[75],"flip-flop":[76],"spatial":[78],"correlations,":[80],"constraints,":[87],"we":[88,120],"solve":[89,121],"assigning":[93,100],"sink":[97],"buffer":[98],"(i.e.,":[99],"type)":[103],"so":[104],"that":[105,146,200],"minimized":[110],"while":[111],"satisfying":[112],"constraints.":[118],"Specifically,":[119],"in":[124,128,163,183],"two":[125],"steps":[126],"where":[127],"step":[129,164,184],"1,":[130],"for":[131],"pair":[133],"sinks":[135,145,177],"set":[137],"feasible":[139,180],"combination(s)":[140],"polarities":[142,175],"do":[147],"not":[148,234],"violate":[149],"constraint":[152,159],"as":[153,155],"well":[154],"extracted,":[161],"2,":[165],"stepwise":[167],"greedy":[168],"method":[169],"applied":[171],"determine":[173],"sets":[181],"obtained":[182],"1":[185],"minimize":[187],"noise.":[190],"Through":[191],"experiments":[192],"ISCAS89":[194],"benchmark":[195],"circuits,":[196],"it":[197],"shown":[199],"our":[201],"proposed":[202],"approach":[203,231],"able":[205],"improve":[207],"by":[209,226],"6.7%":[210],"average":[212],"even":[213],"4.3%":[215],"less":[216,220],"power":[217],"4.4%":[219],"ground":[221],"noises":[222],"over":[223],"results":[225],"conventional":[228],"assignment":[230],"does":[233],"consider":[235],"variations.":[238]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
