{"id":"https://openalex.org/W2167811617","doi":"https://doi.org/10.1109/isqed.2009.4810384","title":"A generalized V-shaped multilevel method for large scale floorplanning","display_name":"A generalized V-shaped multilevel method for large scale floorplanning","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2167811617","doi":"https://doi.org/10.1109/isqed.2009.4810384","mag":"2167811617"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810384","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100423614","display_name":"Song Chen","orcid":"https://orcid.org/0000-0003-0341-3428"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Song Chen","raw_affiliation_strings":["Graduate School of Information, Production, and System, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production, and System, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079303257","display_name":"Zheng Xu","orcid":"https://orcid.org/0000-0003-1283-6238"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Zheng Xu","raw_affiliation_strings":["Graduate School of Information, Production, and System, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production, and System, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101886411","display_name":"Takeshi Yoshimura","orcid":"https://orcid.org/0000-0002-7147-4225"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takeshi Yoshimura","raw_affiliation_strings":["Graduate School of Information, Production, and System, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production, and System, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100423614"],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":0.2991,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.661226,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"734","last_page":"739"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9770159721374512},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6337461471557617},{"id":"https://openalex.org/keywords/partition","display_name":"Partition (number theory)","score":0.5969470143318176},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5890733599662781},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5819612145423889},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5525949001312256},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5432506799697876},{"id":"https://openalex.org/keywords/slicing","display_name":"Slicing","score":0.5302640199661255},{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.49129360914230347},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.469475120306015},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.43679118156433105},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3231011927127838},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.32101958990097046},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3170550465583801},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.29819512367248535}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9770159721374512},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6337461471557617},{"id":"https://openalex.org/C42812","wikidata":"https://www.wikidata.org/wiki/Q1082910","display_name":"Partition (number theory)","level":2,"score":0.5969470143318176},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5890733599662781},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5819612145423889},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5525949001312256},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5432506799697876},{"id":"https://openalex.org/C2776190703","wikidata":"https://www.wikidata.org/wiki/Q488148","display_name":"Slicing","level":2,"score":0.5302640199661255},{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.49129360914230347},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.469475120306015},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.43679118156433105},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3231011927127838},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.32101958990097046},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3170550465583801},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.29819512367248535},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2009.4810384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810384","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","score":0.5799999833106995,"id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1993038918","https://openalex.org/W2078174680","https://openalex.org/W2094042791","https://openalex.org/W2095550547","https://openalex.org/W2100740271","https://openalex.org/W2114772983","https://openalex.org/W2119899316","https://openalex.org/W2120970098","https://openalex.org/W2123354623","https://openalex.org/W2129355781","https://openalex.org/W2129701824","https://openalex.org/W2132915653","https://openalex.org/W2135118255","https://openalex.org/W2135685510","https://openalex.org/W2141235761","https://openalex.org/W2141746747","https://openalex.org/W2153227646","https://openalex.org/W2154462472","https://openalex.org/W2155230244","https://openalex.org/W2163517325","https://openalex.org/W2165891825","https://openalex.org/W2170967477","https://openalex.org/W3142416893","https://openalex.org/W4241903622","https://openalex.org/W4256007160","https://openalex.org/W6682794600","https://openalex.org/W6683833668"],"related_works":["https://openalex.org/W2157271968","https://openalex.org/W2158448234","https://openalex.org/W2004655383","https://openalex.org/W1523582517","https://openalex.org/W1984375234","https://openalex.org/W2115502122","https://openalex.org/W2138401961","https://openalex.org/W2162365765","https://openalex.org/W2353155791","https://openalex.org/W2109972882"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,48,65,102],"propose":[4],"a":[5,31,67,97,142],"generalized":[6],"V-shaped":[7],"multilevel":[8,27,98],"floorplanning":[9,37],"method":[10,28],"with":[11,115,131],"consideration":[12],"of":[13,70,88],"fixed-outline":[14,127],"constraint.":[15],"The":[16,25],"Sequence":[17],"Pair":[18],"is":[19],"used":[20],"as":[21],"the":[22,45,53,89,93,105,112,123],"floorplan":[23,52,74],"representation.":[24],"proposed":[26],"(ML-IARFP)":[29],"adopts":[30],"two-stage":[32],"structure:":[33],"top-down":[34],"partitioning":[35],"and":[36,42,51,110,119,129,140],"followed":[38],"by":[39],"bottom-up":[40],"merging":[41],"refinement.":[43,113],"At":[44,92],"first":[46],"stage,":[47,95],"recursively":[49,103],"partition":[50],"circuits":[54,109],"until":[55],"there":[56],"are":[57,76],"limited":[58],"number":[59],"blocks":[60],"in":[61,78],"each":[62,79],"sub-circuit.":[63],"Since":[64],"use":[66],"multi-partitioning":[68],"instead":[69],"bi-partitioning,":[71],"general":[72],"non-slicing":[73],"structures":[75],"explored":[77],"level,":[80],"which":[81],"potentially":[82],"lead":[83],"to":[84],"more":[85],"effective":[86],"exploration":[87],"solution":[90],"space.":[91],"second":[94],"using":[96],"sequence":[99],"pair":[100],"structure,":[101],"merge":[104],"sub-circuits":[106],"into":[107],"bigger":[108],"do":[111],"Compared":[114],"IMF,":[116],"Capo":[117],"10.2":[118],"IARFP,":[120,132],"ML-IARFP":[121],"obtained":[122],"best":[124],"results":[125],"under":[126],"constraints,":[128],"compared":[130],"it":[133],"achieved":[134],"9%":[135],"wirelength":[136],"reduction":[137],"on":[138],"average":[139],"showed":[141],"better":[143],"scalability.":[144]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}