{"id":"https://openalex.org/W2112595964","doi":"https://doi.org/10.1109/isqed.2009.4810360","title":"Zero clock skew synchronization with rotary clocking technology","display_name":"Zero clock skew synchronization with rotary clocking technology","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2112595964","doi":"https://doi.org/10.1109/isqed.2009.4810360","mag":"2112595964"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810360","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810360","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072530511","display_name":"Vinayak Honkote","orcid":null},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Vinayak Honkote","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104 USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104 USA#TAB#","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104 USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104 USA#TAB#","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072530511"],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":1.7945,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.85929754,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"588","last_page":"593"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.857845664024353},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.8057911396026611},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7918177843093872},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7205981612205505},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6945966482162476},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.6720077991485596},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6189846992492676},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.6178918480873108},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5782451629638672},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5708409547805786},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5313758254051208},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.515712559223175},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4956423044204712},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4479948878288269},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.41649648547172546},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.41070806980133057},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3700132966041565},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27538448572158813},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.169918954372406},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08864906430244446}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.857845664024353},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.8057911396026611},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7918177843093872},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7205981612205505},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6945966482162476},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.6720077991485596},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6189846992492676},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.6178918480873108},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5782451629638672},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5708409547805786},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5313758254051208},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.515712559223175},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4956423044204712},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4479948878288269},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.41649648547172546},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.41070806980133057},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3700132966041565},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27538448572158813},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.169918954372406},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08864906430244446}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2009.4810360","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810360","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1505272351","https://openalex.org/W1585683917","https://openalex.org/W1984588379","https://openalex.org/W1984845646","https://openalex.org/W2022759987","https://openalex.org/W2049078776","https://openalex.org/W2063803683","https://openalex.org/W2122724421","https://openalex.org/W2138857663","https://openalex.org/W2141603529","https://openalex.org/W2144402314","https://openalex.org/W2155670163","https://openalex.org/W2166694777","https://openalex.org/W2166738086","https://openalex.org/W4255697594","https://openalex.org/W6630124008"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2090213929","https://openalex.org/W2617666058","https://openalex.org/W2169618112","https://openalex.org/W2165139624","https://openalex.org/W2803012234","https://openalex.org/W3013924136","https://openalex.org/W2117541676"],"abstract_inverted_index":{"Rotary":[0],"clocking":[1,5,51],"is":[2,53,64,116],"a":[3,9,39,108],"resonant":[4],"technology":[6,52],"that":[7,66,87],"provides":[8],"low-power,":[10],"low-jitter":[11],"clock":[12,24,41,57,68,78,90,104],"signal":[13,25],"with":[14,76,96],"controllable":[15],"skew.":[16],"Due":[17],"to":[18,38,85],"the":[19,23,27,33,46,49,54,88,100,113],"\"rotary\"":[20],"traveling":[21],"of":[22,45,48,102],"on":[26,32,120],"ring":[28,35],"interconnect,":[29],"each":[30],"location":[31],"rotary":[34,50,77,103],"network":[36],"leads":[37],"different":[40],"phase.":[42],"Consequently,":[43],"one":[44],"features":[47],"inherent":[55],"non-zero":[56],"skew":[58,69,91],"operation.":[59,105],"In":[60,106],"this":[61],"paper,":[62],"it":[63],"shown":[65],"zero":[67,89],"circuits":[70],"can":[71,93],"also":[72],"be":[73,94],"efficiently":[74],"implemented":[75],"synchronization.":[79],"Design":[80],"automation":[81],"experiments":[82,119],"are":[83],"performed":[84],"demonstrate":[86],"operation":[92],"achieved":[95],"minimal":[97],"change":[98,111],"in":[99,112,118],"performance":[101],"particular,":[107],"marginal":[109],"plusmn1.5%":[110],"tapping":[114],"wirelength":[115],"reported":[117],"R1-R5":[121],"benchmark":[122],"circuits.":[123]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
