{"id":"https://openalex.org/W2133071611","doi":"https://doi.org/10.1109/isqed.2009.4810351","title":"VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models","display_name":"VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2133071611","doi":"https://doi.org/10.1109/isqed.2009.4810351","mag":"2133071611"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810351","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810351","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047132828","display_name":"Shu-Hsuan Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Shu-Hsuan Chou","raw_affiliation_strings":["Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111936878","display_name":"Che-Neng Wen","orcid":null},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Che-Neng Wen","raw_affiliation_strings":["Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100644013","display_name":"Yanling Liu","orcid":"https://orcid.org/0000-0002-1799-8044"},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yan-Ling Liu","raw_affiliation_strings":["Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056256074","display_name":"Tien-Fu Chen","orcid":"https://orcid.org/0000-0001-6925-893X"},"institutions":[{"id":"https://openalex.org/I148099254","display_name":"National Chung Cheng University","ror":"https://ror.org/0028v3876","country_code":"TW","type":"education","lineage":["https://openalex.org/I148099254"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tien-Fu Chen","raw_affiliation_strings":["Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of CSIE, National Chung Cheng University, Chiayi, Taiwan","institution_ids":["https://openalex.org/I148099254"]},{"raw_affiliation_string":"Dept. of CSIE, National Chung Cheng University, Chia-Yi, Taiwan, R.O.C","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5047132828"],"corresponding_institution_ids":["https://openalex.org/I148099254"],"apc_list":null,"apc_paid":null,"fwci":0.5276,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68692649,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"535","last_page":"540"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9637161493301392},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.902228593826294},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8307490348815918},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6697163581848145},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.6281757354736328},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.5372085571289062},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5345157384872437},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5234643816947937},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5132207870483398},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5053210854530334},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.44681739807128906},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3606908917427063}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9637161493301392},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.902228593826294},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8307490348815918},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6697163581848145},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.6281757354736328},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.5372085571289062},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5345157384872437},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5234643816947937},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5132207870483398},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5053210854530334},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44681739807128906},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3606908917427063}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2009.4810351","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810351","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Life below water","id":"https://metadata.un.org/sdg/14"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1607765501","https://openalex.org/W2094920868","https://openalex.org/W2117572946","https://openalex.org/W2153441705","https://openalex.org/W2157706085","https://openalex.org/W2163033792","https://openalex.org/W2295627138","https://openalex.org/W4231883108"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2069603759","https://openalex.org/W2533881872","https://openalex.org/W2266880325","https://openalex.org/W2097331811","https://openalex.org/W1831349210","https://openalex.org/W2548514518","https://openalex.org/W2133071611","https://openalex.org/W2133642747","https://openalex.org/W1603163876"],"abstract_inverted_index":{"Electronic":[0],"System":[1],"Level":[2],"(ESL)":[3],"is":[4,97,164],"regarded":[5],"as":[6],"a":[7,54,58,108,133,177,192,237],"necessary":[8],"solution":[9],"to":[10,57,72,89,112,137,146,166,170,176],"deal":[11],"with":[12,128,153],"the":[13,26,43,70,73,105,119,172,200,212,224,227,252],"ever":[14],"increasingly":[15],"complex":[16],"System-on-Chip":[17],"(SoC)":[18],"design.":[19,76],"Most":[20],"ESL":[21,60,91,203],"designs":[22],"are":[23,40],"modeling":[24,134],"at":[25,122],"C":[27,33,48],"high-level":[28],"language":[29,83],"(no":[30],"matter":[31],"functional":[32],"or":[34,49],"SystemC).":[35],"Although":[36],"some":[37],"commercial":[38],"products":[39],"partially":[41],"available,":[42],"lack":[44],"of":[45,223,233],"directly":[46,144],"translating":[47],"SystemC":[50],"into":[51],"RTL":[52,67,147,173,206],"becomes":[53],"main":[55],"obstacle":[56],"seamless":[59],"flow":[61],"from":[62],"high":[63],"level":[64,179],"abstraction":[65],"through":[66],"and":[68,87,92,101,125,148,194,205,236],"all":[69],"way":[71,135],"final":[74],"chip":[75],"We":[77],"propose":[78],"an":[79,129],"efficient":[80,196],"semi-hardware":[81],"description":[82],"called":[84],"VeriC":[85,96,140,213],"(Verilog":[86],"C)":[88],"bridge":[90],"RTL.":[93],"Like":[94],"SystemC,":[95,168,221],"based":[98],"on":[99],"C++":[100],"not":[102,165],"only":[103],"describes":[104],"design":[106,121,204],"by":[107,159],"syntax":[109],"very":[110],"close":[111],"Verilog,":[113],"but":[114,169],"also":[115,149,243],"it":[116],"can":[117,142,150,185,216,242],"model":[118,174],"target":[120],"both":[123],"pin":[124],"cycle":[126,239],"accuracy":[127],"implicit":[130],"clock":[131],"mechanism,":[132],"closer":[136],"Verilog.":[138],"Those":[139],"modules":[141,155],"be":[143,151,186,217],"translatable":[145],"interoperable":[152],"other":[154],"in":[156,189,226,250],"C/SystemC/Verilog":[157],"languages":[158],"hybrid":[160],"simulation.":[161],"Our":[162],"objective":[163],"replace":[167],"move":[171],"up":[175],"higher":[178],"such":[180],"that":[181,211],"detailed":[182],"cycle-accurate":[183],"implementation":[184],"present":[187],"even":[188],"C-level":[190],"simulation,":[191],"supplemental":[193],"more":[195],"approach":[197],"for":[198],"bridging":[199],"gap":[201],"between":[202],"models.":[207],"Experimental":[208],"results":[209],"show":[210],"simulation":[214,228,246],"speed":[215],"2-10X":[218],"faster":[219],"than":[220,248],"because":[222],"improvement":[225],"kernel":[229],"(by":[230],"taking":[231],"advantages":[232],"input/output":[234],"connections":[235],"simpler":[238],"mechanism).":[240],"It":[241],"reach":[244],"10X-250X":[245],"speedup":[247],"Verilog":[249],"simulating":[251],"same":[253],"behavior.":[254]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
