{"id":"https://openalex.org/W2126918112","doi":"https://doi.org/10.1109/isqed.2009.4810348","title":"Implementation of power managed hyper transport system for transmission of HD video","display_name":"Implementation of power managed hyper transport system for transmission of HD video","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2126918112","doi":"https://doi.org/10.1109/isqed.2009.4810348","mag":"2126918112"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018635020","display_name":"Adithya V. Kodati","orcid":null},"institutions":[{"id":"https://openalex.org/I51504820","display_name":"San Jose State University","ror":"https://ror.org/04qyvz380","country_code":"US","type":"education","lineage":["https://openalex.org/I51504820"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Adithya V. Kodati","raw_affiliation_strings":["Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","San Jose State University,Dept of Electrical Engineering,CA,USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","institution_ids":["https://openalex.org/I51504820"]},{"raw_affiliation_string":"San Jose State University,Dept of Electrical Engineering,CA,USA","institution_ids":["https://openalex.org/I51504820"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047160258","display_name":"Koneswara S. Vemuri","orcid":null},"institutions":[{"id":"https://openalex.org/I51504820","display_name":"San Jose State University","ror":"https://ror.org/04qyvz380","country_code":"US","type":"education","lineage":["https://openalex.org/I51504820"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Koneswara S. Vemuri","raw_affiliation_strings":["Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","San Jose State University,Dept of Electrical Engineering,CA,USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","institution_ids":["https://openalex.org/I51504820"]},{"raw_affiliation_string":"San Jose State University,Dept of Electrical Engineering,CA,USA","institution_ids":["https://openalex.org/I51504820"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052277806","display_name":"L. He","orcid":"https://orcid.org/0000-0002-7053-0838"},"institutions":[{"id":"https://openalex.org/I51504820","display_name":"San Jose State University","ror":"https://ror.org/04qyvz380","country_code":"US","type":"education","lineage":["https://openalex.org/I51504820"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lili He","raw_affiliation_strings":["Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","San Jose State University,Dept of Electrical Engineering,CA,USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","institution_ids":["https://openalex.org/I51504820"]},{"raw_affiliation_string":"San Jose State University,Dept of Electrical Engineering,CA,USA","institution_ids":["https://openalex.org/I51504820"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102947957","display_name":"Morris E. Jones","orcid":"https://orcid.org/0000-0001-5418-9329"},"institutions":[{"id":"https://openalex.org/I51504820","display_name":"San Jose State University","ror":"https://ror.org/04qyvz380","country_code":"US","type":"education","lineage":["https://openalex.org/I51504820"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Morris Jones","raw_affiliation_strings":["Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","San Jose State University,Dept of Electrical Engineering,CA,USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, San Jose State University Foundation, San Jose, CA, USA","institution_ids":["https://openalex.org/I51504820"]},{"raw_affiliation_string":"San Jose State University,Dept of Electrical Engineering,CA,USA","institution_ids":["https://openalex.org/I51504820"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5018635020"],"corresponding_institution_ids":["https://openalex.org/I51504820"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14287124,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"517","last_page":"521"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9413999915122986,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9413999915122986,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9412999749183655,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12238","display_name":"Green IT and Sustainability","score":0.9283999800682068,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7386462092399597},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.6311459541320801},{"id":"https://openalex.org/keywords/modelsim","display_name":"ModelSim","score":0.5879144668579102},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.5747759342193604},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.48616310954093933},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.4586707353591919},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.45653825998306274},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4469550549983978},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40703344345092773},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.298160195350647},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.2425900399684906},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1253243088722229}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7386462092399597},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6311459541320801},{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.5879144668579102},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.5747759342193604},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.48616310954093933},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.4586707353591919},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.45653825998306274},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4469550549983978},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40703344345092773},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.298160195350647},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2425900399684906},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1253243088722229},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2009.4810348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2347617805","https://openalex.org/W2389765791","https://openalex.org/W2786773189","https://openalex.org/W2377898907","https://openalex.org/W2376047108","https://openalex.org/W2087719824","https://openalex.org/W2622925720","https://openalex.org/W4233287471","https://openalex.org/W2377135490","https://openalex.org/W4281629491"],"abstract_inverted_index":{"Hyper":[0],"transport":[1,89],"is":[2,55,73,81,100,114,142,147,175],"a":[3,85],"bidirectional,":[4],"serial/parallel":[5],"high":[6,96],"bandwidth,":[7],"low":[8,66],"latency,":[9],"point-to-point":[10],"interface":[11,32],"architecture.":[12],"In":[13],"this":[14],"architecture,":[15],"data":[16,37,118,130,137,165],"can":[17,34,64,155],"be":[18,156],"sent":[19],"on":[20],"both":[21],"rising":[22],"and":[23,59,63,120,138,146],"falling":[24],"edges":[25],"of":[26,95,163,171],"the":[27,36,42,49,77,93,104,125,134,152],"clock":[28],"making":[29],"it":[30,122,154],"an":[31,167],"that":[33,45,158],"transmit":[35],"faster":[38],"when":[39,71,112],"compared":[40],"to":[41,83,109,124],"other":[43],"architectures":[44],"are":[46],"available":[47],"in":[48,76,144],"market":[50],"today.":[51],"This":[52,79,140],"architecture":[53],"also":[54],"ACPI":[56],"(advanced":[57],"configuration":[58],"power":[60,67,86,169],"interface)":[61],"compliant":[62],"provide":[65],"by":[68,102],"switching":[69,103,121],"off":[70],"there":[72,113],"no":[74,115],"activity":[75],"system.":[78],"project":[80,141],"aimed":[82],"develop":[84],"managed":[87,101],"hyper":[88],"system":[90,105],"prototype":[91],"for":[92],"transmission":[94],"definition":[97],"video.":[98],"Power":[99],"from":[106],"active":[107,126],"state":[108,111,127],"sleep":[110],"heavy":[116],"isochronous":[117,129,164],"flowing":[119],"back":[123],"before":[128],"arrives,":[131],"while":[132],"by-passing":[133],"prioritized":[135],"video":[136],"interrupts.":[139],"implemented":[143],"Verilog":[145],"simulated":[148],"using":[149],"ModelSim.":[150],"From":[151],"simulations,":[153],"observed":[157],"at":[159],"50%":[160],"-":[161,173],"70%":[162],"transfer":[166],"overall":[168],"saving":[170],"20%":[172],"40%":[174],"achieved.":[176]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}