{"id":"https://openalex.org/W2164067134","doi":"https://doi.org/10.1109/isqed.2009.4810339","title":"Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit","display_name":"Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2164067134","doi":"https://doi.org/10.1109/isqed.2009.4810339","mag":"2164067134"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054957806","display_name":"Xin He","orcid":"https://orcid.org/0000-0001-6983-3834"},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xin He","raw_affiliation_strings":["University of California Riverside, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California Riverside, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009484623","display_name":"Syed Al-Kadry","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Syed Al-Kadry","raw_affiliation_strings":["University of California Riverside, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California Riverside, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109214532","display_name":"Afshin Abdollahi","orcid":null},"institutions":[{"id":"https://openalex.org/I103635307","display_name":"University of California, Riverside","ror":"https://ror.org/03nawhv43","country_code":"US","type":"education","lineage":["https://openalex.org/I103635307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Afshin Abdollahi","raw_affiliation_strings":["University of California Riverside, Riverside, CA, USA"],"affiliations":[{"raw_affiliation_string":"University of California Riverside, Riverside, CA, USA","institution_ids":["https://openalex.org/I103635307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5054957806"],"corresponding_institution_ids":["https://openalex.org/I103635307"],"apc_list":null,"apc_paid":null,"fwci":1.1963,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.81806756,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"465","last_page":"470"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7456124424934387},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.6305038928985596},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6267497539520264},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.6177536249160767},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6171744465827942},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5732834935188293},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.5525192022323608},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5381290912628174},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.49878740310668945},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4763365387916565},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4151843190193176},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.33772891759872437},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2469836175441742},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11992400884628296}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7456124424934387},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.6305038928985596},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6267497539520264},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.6177536249160767},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6171744465827942},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5732834935188293},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.5525192022323608},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5381290912628174},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.49878740310668945},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4763365387916565},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4151843190193176},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.33772891759872437},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2469836175441742},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11992400884628296},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2009.4810339","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810339","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9200000166893005,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2011188087","https://openalex.org/W2114967216","https://openalex.org/W2121882537","https://openalex.org/W2145071646","https://openalex.org/W2170444169"],"related_works":["https://openalex.org/W2069427488","https://openalex.org/W4281694563","https://openalex.org/W2080696413","https://openalex.org/W2163182355","https://openalex.org/W1506140395","https://openalex.org/W4232799642","https://openalex.org/W2491872651","https://openalex.org/W3022979525","https://openalex.org/W1920602296","https://openalex.org/W2074584731"],"abstract_inverted_index":{"Power":[0],"dissipation":[1,25,80],"is":[2,39,110],"an":[3],"important":[4],"issue":[5],"in":[6,41,84],"VLSI":[7,106],"circuit":[8,62,90,124],"design.":[9],"This":[10],"paper":[11],"emphasizes":[12],"on":[13],"adaptive":[14],"leakage":[15,38],"control":[16],"using":[17],"body":[18,35,117],"bias":[19,118],"technique":[20],"to":[21,76,101,111,119,125],"reduce":[22,77,102,120],"the":[23,27,37,53,58,61,67,78,89,95,99,113,116,123,130],"power":[24,79,103,128],"of":[26,105,115],"65":[28],"nm":[29,43,48],"MOS":[30],"devices.":[31],"Through":[32],"adding":[33],"forward":[34],"biasing,":[36],"reduced":[40],"sub-100":[42],"CMOS":[44],"devices":[45],"(unlike":[46],"above-100":[47],"devices)":[49],"while":[50],"slightly":[51],"increasing":[52],"signal":[54],"propagation":[55],"delay.":[56],"For":[57],"conditions":[59],"where":[60],"does":[63],"not":[64],"use":[65],"up":[66],"entire":[68],"clock":[69,96,131],"cycle,":[70],"this":[71],"slack":[72],"can":[73,133],"be":[74,134],"used":[75],"without":[81],"any":[82],"loss":[83],"performance.":[85],"The":[86,108],"fact":[87],"that":[88],"delay":[91],"remains":[92],"less":[93,127],"than":[94],"period":[97],"provides":[98],"opportunity":[100],"consumption":[104],"circuits.":[107],"objective":[109],"change":[112],"voltage":[114],"leakage,":[121],"allowing":[122],"consume":[126],"whenever":[129],"edge":[132],"met":[135],"as":[136],"detected":[137],"beforehand.":[138]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}