{"id":"https://openalex.org/W2144613608","doi":"https://doi.org/10.1109/isqed.2009.4810315","title":"Switch level optimization of digital CMOS gate networks","display_name":"Switch level optimization of digital CMOS gate networks","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2144613608","doi":"https://doi.org/10.1109/isqed.2009.4810315","mag":"2144613608"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]},{"id":"https://openalex.org/I110676245","display_name":"Universidade Cat\u00f3lica de Pelotas","ror":"https://ror.org/0376myh60","country_code":"BR","type":"education","lineage":["https://openalex.org/I110676245"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Leomar S. da Rosa","raw_affiliation_strings":["Departamento de Informe#x00E1;tica, UFPel, Pelotas, Rio Grande do Sul, Brazil","tica, UFPel, Pelotas, Rio Grande do Sul, Brazil","Departamento de Informe#x00E1"],"affiliations":[{"raw_affiliation_string":"Departamento de Informe#x00E1;tica, UFPel, Pelotas, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I110676245","https://openalex.org/I169248161"]},{"raw_affiliation_string":"tica, UFPel, Pelotas, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Departamento de Informe#x00E1","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067885070","display_name":"Felipe Ribeiro Schneider","orcid":null},"institutions":[{"id":"https://openalex.org/I131787340","display_name":"Seagate (United States)","ror":"https://ror.org/04p1xtv71","country_code":"US","type":"company","lineage":["https://openalex.org/I131787340"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Felipe R. Schneider","raw_affiliation_strings":["Nangate, Inc., Menlo Park, CA, USA"],"affiliations":[{"raw_affiliation_string":"Nangate, Inc., Menlo Park, CA, USA","institution_ids":["https://openalex.org/I131787340"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I4210147991","display_name":"Instituto de Informaci\u00f3n Cient\u00ed\ufb01ca y Tecnol\u00f3gica","ror":"https://ror.org/05m8k7t58","country_code":"CU","type":"facility","lineage":["https://openalex.org/I4210147991"]},{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR","CU"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["Instituto de Informe#x00E0;tica, UFRGS, Porto Alegre, Rio Grande do Sul, Brazil","Instituto de Informe#x00E0","tica, UFRGS, Porto Alegre, Rio Grande do Sul, Brazil"],"affiliations":[{"raw_affiliation_string":"Instituto de Informe#x00E0;tica, UFRGS, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]},{"raw_affiliation_string":"Instituto de Informe#x00E0","institution_ids":["https://openalex.org/I4210147991"]},{"raw_affiliation_string":"tica, UFRGS, Porto Alegre, Rio Grande do Sul, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I131787340","display_name":"Seagate (United States)","ror":"https://ror.org/04p1xtv71","country_code":"US","type":"company","lineage":["https://openalex.org/I131787340"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andre I. Reis","raw_affiliation_strings":["Nangate, Inc., Menlo Park, CA, USA"],"affiliations":[{"raw_affiliation_string":"Nangate, Inc., Menlo Park, CA, USA","institution_ids":["https://openalex.org/I131787340"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5014303947"],"corresponding_institution_ids":["https://openalex.org/I110676245","https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":2.6917,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.90519206,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"324","last_page":"329"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7193801403045654},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7184554934501648},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6017612814903259},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5690805912017822},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5255326628684998},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.4735778272151947},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.42356839776039124},{"id":"https://openalex.org/keywords/quality","display_name":"Quality (philosophy)","score":0.41043317317962646},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24888041615486145},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2201162576675415},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07750436663627625}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7193801403045654},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7184554934501648},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6017612814903259},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5690805912017822},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5255326628684998},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.4735778272151947},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.42356839776039124},{"id":"https://openalex.org/C2779530757","wikidata":"https://www.wikidata.org/wiki/Q1207505","display_name":"Quality (philosophy)","level":2,"score":0.41043317317962646},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24888041615486145},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2201162576675415},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07750436663627625},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2009.4810315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality of Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1479741658","https://openalex.org/W1546585099","https://openalex.org/W1580033321","https://openalex.org/W1891500466","https://openalex.org/W1963548198","https://openalex.org/W1968414338","https://openalex.org/W2073840571","https://openalex.org/W2078179095","https://openalex.org/W2088115909","https://openalex.org/W2100350782","https://openalex.org/W2102664288","https://openalex.org/W2114301751","https://openalex.org/W2127856935","https://openalex.org/W2129042422","https://openalex.org/W2129501340","https://openalex.org/W2139352487","https://openalex.org/W2139358663","https://openalex.org/W2149214288","https://openalex.org/W2155214620","https://openalex.org/W2158020817","https://openalex.org/W3144234790","https://openalex.org/W4236571951","https://openalex.org/W4242228517","https://openalex.org/W6675054765"],"related_works":["https://openalex.org/W2198645257","https://openalex.org/W67296738","https://openalex.org/W2290310756","https://openalex.org/W2063994266","https://openalex.org/W1900707063","https://openalex.org/W2039299085","https://openalex.org/W2774773774","https://openalex.org/W2164005033","https://openalex.org/W2167525841","https://openalex.org/W2170979950"],"abstract_inverted_index":{"This":[0,75],"paper":[1],"presents":[2],"a":[3],"comprehensive":[4],"investigation":[5],"of":[6,18,25,35,42,52,86],"how":[7],"transistor":[8,26,54,64,73],"level":[9],"optimizations":[10],"can":[11],"be":[12],"used":[13,29],"to":[14,30],"increase":[15],"design":[16,50],"quality":[17,51],"CMOS":[19],"logic":[20],"gate":[21],"networks.":[22,55,88],"Different":[23],"properties":[24],"networks":[27],"are":[28],"explain":[31],"features":[32],"and":[33],"limitations":[34],"different":[36,60],"methods.":[37],"We":[38],"describe":[39],"which":[40],"figures":[41],"merit,":[43],"including":[44,66],"the":[45,49,83,87],"logical":[46,84],"effort,":[47],"affect":[48],"cell":[53],"Further,":[56],"we":[57],"compare":[58],"six":[59],"approaches":[61],"that":[62,78],"generate":[63],"networks,":[65],"two":[67],"with":[68],"guaranteed":[69],"theoretical":[70],"minimum":[71,79],"length":[72,80],"chains.":[74],"comparison":[76],"shows":[77],"chains":[81],"reduce":[82],"effort":[85]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}