{"id":"https://openalex.org/W2096582236","doi":"https://doi.org/10.1109/isqed.2009.4810268","title":"A PVT aware accurate statistical logic library for high-\u03ba metal-gate nano-CMOS","display_name":"A PVT aware accurate statistical logic library for high-\u03ba metal-gate nano-CMOS","publication_year":2009,"publication_date":"2009-03-01","ids":{"openalex":"https://openalex.org/W2096582236","doi":"https://doi.org/10.1109/isqed.2009.4810268","mag":"2096582236"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2009.4810268","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810268","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065315664","display_name":"Dhruva Ghai","orcid":"https://orcid.org/0000-0002-8204-6330"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dhruva Ghai","raw_affiliation_strings":["VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, TX, USA","VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, 76203, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, 76203, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070359867","display_name":"Saraju P. Mohanty","orcid":"https://orcid.org/0000-0003-2959-6541"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saraju P. Mohanty","raw_affiliation_strings":["VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, TX, USA","VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, 76203, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, 76203, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062843590","display_name":"Elias Kougianos","orcid":"https://orcid.org/0000-0002-1616-7628"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elias Kougianos","raw_affiliation_strings":["VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, TX, USA","VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, 76203, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, 76203, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084851156","display_name":"Priyadarsan Patra","orcid":"https://orcid.org/0000-0002-9585-0598"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Priyadarsan Patra","raw_affiliation_strings":["Validation Research Laboratory, Intel Corporation, Hillsboro, OR, USA","Validation Research Lab, Intel Corporation, Hillsboro, OR 97124, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Validation Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Validation Research Lab, Intel Corporation, Hillsboro, OR 97124, USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4854,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.57386793,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"41","issue":null,"first_page":"47","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4577130675315857},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4514153003692627},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.39451324939727783},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.35383498668670654},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.34392470121383667},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.34005850553512573},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1637740135192871}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4577130675315857},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4514153003692627},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.39451324939727783},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.35383498668670654},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.34392470121383667},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.34005850553512573},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1637740135192871}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2009.4810268","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2009.4810268","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 10th International Symposium on Quality Electronic Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6100000143051147}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W259905952","https://openalex.org/W1499398507","https://openalex.org/W1506818965","https://openalex.org/W1633471522","https://openalex.org/W1761143336","https://openalex.org/W1991622720","https://openalex.org/W2026070520","https://openalex.org/W2107205352","https://openalex.org/W2107265146","https://openalex.org/W2108880814","https://openalex.org/W2114336500","https://openalex.org/W2116359224","https://openalex.org/W2120937992","https://openalex.org/W2126388445","https://openalex.org/W2126862634","https://openalex.org/W2137756359","https://openalex.org/W2142718365","https://openalex.org/W2158055579","https://openalex.org/W2166243422","https://openalex.org/W2169340912","https://openalex.org/W2527370335","https://openalex.org/W2535919346","https://openalex.org/W2539850963","https://openalex.org/W4285719527","https://openalex.org/W6684710031"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2051487156","https://openalex.org/W3014521742","https://openalex.org/W2073681303","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W2171986175","https://openalex.org/W2089791793"],"abstract_inverted_index":{"The":[0],"semiconductor":[1],"industry":[2],"is":[3,27,97,121,124,143],"headed":[4],"towards":[5],"a":[6,28,39,56,149],"new":[7,14],"era":[8],"of":[9,33,41,102,132,138],"scaling":[10],"and":[11,85,119],"uncertainty":[12],"with":[13],"key":[15],"building":[16],"blocks":[17],"for":[18,30,49,58,77,108,128,154],"the":[19,22,68,93,136,139,144],"next-generation":[20],"chips,":[21],"high-kappa":[23,34,61,155],"metal-gate":[24,35,62,156],"transistor.":[25],"There":[26],"need":[29],"statistical":[31,75,100,152],"characterization":[32,101,131,153],"digital":[36],"gates":[37],"as":[38],"function":[40],"process":[42],"parameter":[43],"variations":[44],"to":[45],"make":[46],"them":[47],"available":[48],"designers.":[50],"In":[51],"this":[52,142],"paper,":[53],"we":[54],"present":[55],"methodology":[57],"PVT":[59,129,150],"aware":[60,130,151],"logic":[63,103,133,159],"library":[64],"creation":[65],"while":[66],"considering":[67],"variability":[69],"effect":[70],"in":[71],"15":[72],"parameters.":[73],"First,":[74],"models":[76],"GIDL":[78],"current":[79,87,110,116],"(I":[80,83,88,111,117],"circGIDL),":[81],"offcurrent":[82],"circoff)":[84],"drive":[86],"circON)":[89],"are":[90],"presented":[91],"at":[92,105],"device":[94],"level.":[95],"This":[96,123],"followed":[98,125],"by":[99,126],"cells":[104],"roomtemperature.":[106],"Data":[107],"subthreshold":[109],"circsub),":[112],"I":[113],"circGIDL,":[114],"dynamic":[115],"circdyn)":[118],"delay":[120],"presented.":[122],"results":[127],"cells.":[134],"To":[135],"best":[137],"authors'":[140],"knowledge,":[141],"first":[145],"research":[146],"which":[147],"provides":[148],"nano-CMOS":[157],"based":[158],"gates.":[160]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2013,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
