{"id":"https://openalex.org/W2146948228","doi":"https://doi.org/10.1109/isqed.2008.4479843","title":"On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits","display_name":"On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2146948228","doi":"https://doi.org/10.1109/isqed.2008.4479843","mag":"2146948228"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109153191","display_name":"Amlan Ghosh","orcid":null},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Amlan Ghosh","raw_affiliation_strings":["University of Utah, Salt Lake, UT, USA"],"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103068738","display_name":"Rahul Rao","orcid":"https://orcid.org/0000-0002-7784-7029"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]},{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rahul M. Rao","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","University of Utah, Salt Lake, UT, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111956726","display_name":"Ching-Te Chuang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]},{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ching-Te Chuang","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","University of Utah, Salt Lake, UT, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050281199","display_name":"Richard B. Brown","orcid":"https://orcid.org/0000-0003-2539-2728"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Richard B. Brown","raw_affiliation_strings":["University of Utah, Salt Lake, UT, USA"],"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5109153191"],"corresponding_institution_ids":["https://openalex.org/I223532165"],"apc_list":null,"apc_paid":null,"fwci":2.3306,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.88902765,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"5","issue":null,"first_page":"815","last_page":"820"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.8117834329605103},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.7398686408996582},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.6410906314849854},{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.5889634490013123},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5853016376495361},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5424429178237915},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.5308692455291748},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.5304946899414062},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.46068599820137024},{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.4596931040287018},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.44123750925064087},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.4230040907859802},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.39968740940093994},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.29820847511291504},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29223817586898804},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.29204726219177246},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2503063678741455},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.19046685099601746},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14490193128585815}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.8117834329605103},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.7398686408996582},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.6410906314849854},{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.5889634490013123},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5853016376495361},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5424429178237915},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.5308692455291748},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.5304946899414062},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.46068599820137024},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.4596931040287018},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.44123750925064087},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4230040907859802},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.39968740940093994},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.29820847511291504},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29223817586898804},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.29204726219177246},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2503063678741455},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.19046685099601746},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14490193128585815},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C11171543","wikidata":"https://www.wikidata.org/wiki/Q41630","display_name":"Psychoanalysis","level":1,"score":0.0},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479843","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479843","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.46000000834465027,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1882085838","https://openalex.org/W1999253425","https://openalex.org/W2056796532","https://openalex.org/W2098092384","https://openalex.org/W2101848657","https://openalex.org/W2108127918","https://openalex.org/W2122217504","https://openalex.org/W2122592588","https://openalex.org/W2142410062","https://openalex.org/W2145125899","https://openalex.org/W2150526221","https://openalex.org/W2155470578","https://openalex.org/W6639195530"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W1691923927","https://openalex.org/W2020200124","https://openalex.org/W2380365775","https://openalex.org/W2109891029","https://openalex.org/W2182628752","https://openalex.org/W4211170193","https://openalex.org/W2134944363","https://openalex.org/W1804063983","https://openalex.org/W4229446324"],"abstract_inverted_index":{"In":[0,25],"the":[1,16,22,46,77,81,116,121,125,129,134],"nm":[2,102],"design":[3],"era,":[4],"post-fabrication":[5],"process":[6,19,145],"characterization":[7],"and":[8,32,41,49,53,86,93],"compensation":[9,33,67],"have":[10],"become":[11],"extremely":[12],"important":[13],"for":[14],"mitigating":[15],"impact":[17],"of":[18,48,51,58,61,96,114,120,128,141],"variations":[20],"on":[21,72],"parametric":[23],"yield.":[24],"this":[26],"paper,":[27],"a":[28,100],"new":[29],"variation":[30],"detection":[31,78],"scheme":[34],"is":[35,64],"presented":[36],"that":[37],"uses":[38],"both":[39,60],"slew":[40,75],"delay":[42,73,119,131],"metrics":[43,63],"to":[44,83,111,123],"gauge":[45],"drive-strengths":[47],"mismatch":[50],"NMOS":[52],"PMOS":[54],"devices.":[55],"The":[56],"importance":[57],"considering":[59],"these":[62,97],"illustrated.":[65],"Four":[66],"schemes":[68,98,108],"are":[69,105,109],"analyzed,":[70],"based":[71],"or":[74],"as":[76],"metric,":[79],"with":[80],"ability":[82],"apply":[84],"forward":[85],"reverse":[87],"body-biasing.":[88],"Design":[89],"considerations,":[90],"simulation":[91],"results":[92],"power-performance":[94],"characteristics":[95],"in":[99],"45":[101],"SOI":[103],"technology":[104],"presented.":[106],"These":[107],"shown":[110],"be":[112],"capable":[113],"adjusting":[115],"critical":[117],"path":[118],"die":[122],"within":[124],"desired":[126],"plusmn3%":[127],"nominal":[130],"while":[132],"reducing":[133],"total":[135],"power":[136],"dissipation":[137],"by":[138],"an":[139],"average":[140],"~8%":[142],"across":[143],"various":[144],"corners.":[146]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
