{"id":"https://openalex.org/W1971840499","doi":"https://doi.org/10.1109/isqed.2008.4479840","title":"Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits","display_name":"Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W1971840499","doi":"https://doi.org/10.1109/isqed.2008.4479840","mag":"1971840499"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479840","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479840","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052325166","display_name":"Uthman Alsaiari","orcid":"https://orcid.org/0000-0003-0244-5970"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Uthman Alsaiari","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of British Columbia, Vancouver, Canada","University of British Columbia/Vancouver"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"University of British Columbia/Vancouver","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111377679","display_name":"Resve Saleh","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Resve Saleh","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of British Columbia, Vancouver, Canada","University of British Columbia/Vancouver"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of British Columbia, Vancouver, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"University of British Columbia/Vancouver","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":0.1879,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.35053763,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"798","last_page":"803"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7146892547607422},{"id":"https://openalex.org/keywords/spare-part","display_name":"Spare part","score":0.6693663001060486},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5975262522697449},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5839813351631165},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5511615872383118},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5413789749145508},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.5395327210426331},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.5325457453727722},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5279476046562195},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.49205106496810913},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.48121193051338196},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.46799322962760925},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.4503263235092163},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4058228135108948},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.35509300231933594},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3349260687828064},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3313196301460266},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2698636054992676},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21475523710250854},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1732686460018158},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1101057231426239},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0829584002494812}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7146892547607422},{"id":"https://openalex.org/C194648553","wikidata":"https://www.wikidata.org/wiki/Q1364774","display_name":"Spare part","level":2,"score":0.6693663001060486},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5975262522697449},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5839813351631165},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5511615872383118},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5413789749145508},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.5395327210426331},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.5325457453727722},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5279476046562195},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.49205106496810913},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.48121193051338196},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.46799322962760925},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.4503263235092163},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4058228135108948},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35509300231933594},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3349260687828064},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3313196301460266},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2698636054992676},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21475523710250854},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1732686460018158},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1101057231426239},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0829584002494812},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479840","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479840","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W233723723","https://openalex.org/W1511688816","https://openalex.org/W1558796979","https://openalex.org/W1951775667","https://openalex.org/W2061522142","https://openalex.org/W2072397728","https://openalex.org/W2106935654","https://openalex.org/W2141180409","https://openalex.org/W2161778007","https://openalex.org/W2170254026","https://openalex.org/W2321486756","https://openalex.org/W4302458519","https://openalex.org/W6630623413","https://openalex.org/W6640691897"],"related_works":["https://openalex.org/W2262031297","https://openalex.org/W2024069812","https://openalex.org/W2056378213","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W2163601309","https://openalex.org/W2350494013","https://openalex.org/W4298048893","https://openalex.org/W1965850601","https://openalex.org/W2546023602"],"abstract_inverted_index":{"As":[0],"the":[1,32,35,47,54,78,93,101,105,122,141,179],"number":[2,79,145],"of":[3,31,37,46,58,80,146,170],"transistors":[4,33],"on":[5,53,83,175],"a":[6,29,96],"chip":[7],"begins":[8,18],"to":[9,16,19,27,68,76,99,118],"exceed":[10],"1":[11],"billion":[12],"and":[13,41,56,61,85,107,131,156,160,163,183],"their":[14,62],"sensitivity":[15],"defects":[17],"degrade":[20],"overall":[21,142],"yield,":[22],"it":[23,134],"will":[24],"be":[25],"mandatory":[26],"assign":[28],"portion":[30],"for":[34],"purposes":[36],"built-in-":[38],"self-test":[39,55],"(BIST)":[40],"built-in-self-repair":[42],"(BISR)":[43],"as":[44],"part":[45],"supporting":[48],"circuitry.":[49],"Here,":[50],"we":[51,91,112],"focus":[52],"self-repair":[57],"flip-flops":[59,94],"(FF's),":[60],"associated":[63],"interconnect,":[64],"using":[65],"spare":[66],"FF's":[67],"replace":[69],"faulty":[70],"ones.":[71],"We":[72],"describe":[73],"our":[74,171],"method":[75,172],"determine":[77],"spares":[81],"based":[82],"delay":[84,106],"yield":[86,102,180],"analysis.":[87],"Using":[88],"these":[89],"results,":[90],"partition":[92],"in":[95,121,140],"sequential":[97,147],"design":[98],"improve":[100],"while":[103,177],"keeping":[104],"area":[108,168],"overhead":[109,169],"low.":[110],"Next,":[111],"apply":[113],"this":[114],"redundancy":[115],"approach":[116],"only":[117],"non-critical":[119],"paths":[120],"circuit":[123],"so":[124],"that":[125,133],"no":[126,185],"timing":[127,186],"penalty":[128],"is":[129,173],"incurred,":[130],"find":[132],"can":[135],"still":[136],"provide":[137],"significant":[138],"improvement":[139],"yield.":[143],"A":[144],"benchmark":[148],"circuits":[149],"from":[150],"ITC":[151],"'99":[152],"are":[153],"compared":[154],"with":[155,162],"without":[157,164],"redundant":[158],"flip-flops,":[159],"also":[161],"partitioning.":[165],"The":[166],"total":[167],"8%":[174],"average":[176],"improving":[178],"by":[181],"6-29%":[182],"incurring":[184],"penalty.":[187]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
