{"id":"https://openalex.org/W2136922322","doi":"https://doi.org/10.1109/isqed.2008.4479835","title":"An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node","display_name":"An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2136922322","doi":"https://doi.org/10.1109/isqed.2008.4479835","mag":"2136922322"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479835","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063008784","display_name":"Chin-Khai Tang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chin-Khai Tang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","National Taiwan University, Taipei,"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"National Taiwan University, Taipei,","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103616260","display_name":"Chun-Yen Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chun-Yen Lin","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","National Taiwan University, Taipei,"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"National Taiwan University, Taipei,","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040956103","display_name":"Yi-Chang Lu","orcid":"https://orcid.org/0000-0002-7638-0367"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Chang Lu","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","National Taiwan University, Taipei,"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"National Taiwan University, Taipei,","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5063008784"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":1.6647,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.85045523,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"769","last_page":"773"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/handshaking","display_name":"Handshaking","score":0.8431509137153625},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7447933554649353},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7310829758644104},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6908858418464661},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6209105253219604},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5683603286743164},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48566997051239014},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4667634665966034},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4622156023979187},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.4343961477279663},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.4315488636493683},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4016066789627075},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3227083384990692},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1997358500957489},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18268966674804688},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1683131754398346},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16070404648780823},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12053138017654419},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11609873175621033},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.0788595974445343}],"concepts":[{"id":"https://openalex.org/C58861099","wikidata":"https://www.wikidata.org/wiki/Q548838","display_name":"Handshaking","level":2,"score":0.8431509137153625},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7447933554649353},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7310829758644104},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6908858418464661},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6209105253219604},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5683603286743164},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48566997051239014},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4667634665966034},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4622156023979187},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.4343961477279663},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.4315488636493683},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4016066789627075},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3227083384990692},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1997358500957489},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18268966674804688},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1683131754398346},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16070404648780823},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12053138017654419},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11609873175621033},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0788595974445343},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479835","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479835","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W270615609","https://openalex.org/W1527137186","https://openalex.org/W1600133697","https://openalex.org/W2059193309","https://openalex.org/W2106545930","https://openalex.org/W2108964809"],"related_works":["https://openalex.org/W4231158717","https://openalex.org/W2059009651","https://openalex.org/W3174071739","https://openalex.org/W2150513440","https://openalex.org/W4254482168","https://openalex.org/W18274992","https://openalex.org/W2098328611","https://openalex.org/W2100009051","https://openalex.org/W2168226525","https://openalex.org/W2045506892"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3],"new":[4],"asynchronous":[5,39,65],"circuit":[6],"design":[7],"is":[8,17],"presented.":[9],"A":[10],"special":[11],"technique":[12],"that":[13],"enables":[14],"fast":[15],"forwarding":[16],"applied":[18],"to":[19,27,69,76],"the":[20,23,38,70],"circuits,":[21],"and":[22,34,43,46,50,72,81],"forward":[24],"transition":[25],"improves":[26],"less":[28],"than":[29],"2.":[30],"The":[31,63],"handshaking":[32],"process":[33],"cycle":[35],"time":[36],"of":[37],"circuits":[40,66,75],"are":[41,53,67],"analyzed,":[42],"its":[44],"performance":[45],"functionality":[47],"under":[48],"fabrication":[49],"temperature":[51],"variations":[52,80],"evaluated":[54],"through":[55],"Monte":[56],"Carlo":[57],"simulations":[58],"in":[59],"65":[60],"nm":[61],"technology.":[62],"proposed":[64],"compared":[68],"static":[71],"domino":[73],"logic":[74],"assess":[77],"their":[78],"delay":[79],"functional":[82],"success":[83],"rates.":[84]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}