{"id":"https://openalex.org/W2130690367","doi":"https://doi.org/10.1109/isqed.2008.4479813","title":"Automated Standard Cell Library Analysis for Improved Defect Modeling","display_name":"Automated Standard Cell Library Analysis for Improved Defect Modeling","publication_year":2008,"publication_date":"2008-03-01","ids":{"openalex":"https://openalex.org/W2130690367","doi":"https://doi.org/10.1109/isqed.2008.4479813","mag":"2130690367"},"language":"en","primary_location":{"id":"doi:10.1109/isqed.2008.4479813","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479813","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072477631","display_name":"J.G. Brown","orcid":"https://orcid.org/0000-0002-1235-3722"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"J.G. Brown","raw_affiliation_strings":["Center for Silicon System Implementation Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","Carnegie Mellon University. Pittsburgh"],"affiliations":[{"raw_affiliation_string":"Center for Silicon System Implementation Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon University. Pittsburgh","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111967389","display_name":"R.D. Blanton","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R.D. Blanton","raw_affiliation_strings":["Center for Silicon System Implementation Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","Carnegie Mellon University. Pittsburgh"],"affiliations":[{"raw_affiliation_string":"Center for Silicon System Implementation Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon University. Pittsburgh","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072477631"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.11101589,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"643","last_page":"648"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6943696737289429},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.6337330341339111},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.587120771408081},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.5867159366607666},{"id":"https://openalex.org/keywords/fault-model","display_name":"Fault model","score":0.5474340915679932},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5456975698471069},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5068679451942444},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.505137026309967},{"id":"https://openalex.org/keywords/network-analysis","display_name":"Network analysis","score":0.43503594398498535},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.42732298374176025},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4249236583709717},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41544392704963684},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.38223129510879517},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.37828436493873596},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36688366532325745},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35667684674263},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3047894537448883},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.228645920753479},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.218307226896286},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2083320915699005},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20394599437713623},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1953253149986267},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10487547516822815}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6943696737289429},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.6337330341339111},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.587120771408081},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.5867159366607666},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.5474340915679932},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5456975698471069},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5068679451942444},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.505137026309967},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.43503594398498535},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.42732298374176025},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4249236583709717},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41544392704963684},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.38223129510879517},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.37828436493873596},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36688366532325745},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35667684674263},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3047894537448883},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.228645920753479},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.218307226896286},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2083320915699005},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20394599437713623},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1953253149986267},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10487547516822815},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isqed.2008.4479813","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isqed.2008.4479813","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Symposium on Quality Electronic Design (isqed 2008)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W122496158","https://openalex.org/W323788668","https://openalex.org/W1503570386","https://openalex.org/W1554885925","https://openalex.org/W1632381123","https://openalex.org/W1695545649","https://openalex.org/W1775604791","https://openalex.org/W1908637464","https://openalex.org/W1972403558","https://openalex.org/W1979502538","https://openalex.org/W1986941465","https://openalex.org/W2010065567","https://openalex.org/W2041090186","https://openalex.org/W2046817879","https://openalex.org/W2096007426","https://openalex.org/W2098112833","https://openalex.org/W2102383741","https://openalex.org/W2106290994","https://openalex.org/W2109768518","https://openalex.org/W2110210775","https://openalex.org/W2121147757","https://openalex.org/W2126263957","https://openalex.org/W2130231461","https://openalex.org/W2134332340","https://openalex.org/W2138223068","https://openalex.org/W2139267868","https://openalex.org/W2144225402","https://openalex.org/W2156443301","https://openalex.org/W2157527902","https://openalex.org/W2162442179","https://openalex.org/W2163558178","https://openalex.org/W4302458519","https://openalex.org/W6604992875","https://openalex.org/W6636799148"],"related_works":["https://openalex.org/W2340957901","https://openalex.org/W4256030018","https://openalex.org/W2147400189","https://openalex.org/W1555400249","https://openalex.org/W2031110496","https://openalex.org/W2568949342","https://openalex.org/W2037862379","https://openalex.org/W1519923721","https://openalex.org/W2157154381","https://openalex.org/W4253743993"],"abstract_inverted_index":{"Inductive":[0],"fault":[1,22,116,127],"analysis":[2],"techniques":[3],"examine":[4],"the":[5,31,35,78,102,110,143],"physical":[6,103],"geometry":[7],"of":[8,30,37,63,82,105,145],"a":[9,38,42,57,95,99,106,135],"design":[10],"to":[11,56,77,97],"identify":[12],"potential":[13],"defect":[14],"sites.":[15],"Since":[16],"traditional":[17,146],"methodologies":[18],"for":[19,122,137],"test":[20,147],"generation,":[21],"simulation,":[23],"and":[24,70,109,118],"diagnosis":[25],"rely":[26],"on":[27],"logic-level":[28,58],"models":[29,128],"circuit":[32,39],"under":[33],"test,":[34],"behavior":[36,81],"node":[40],"within":[41],"standard":[43,107],"cell":[44,108],"is":[45],"not":[46,52],"easily":[47],"modeled":[48],"since":[49],"it":[50],"does":[51],"always":[53],"map":[54],"directly":[55],"signal.":[59],"A":[60],"significant":[61],"percentage":[62],"defects,":[64],"however,":[65],"involves":[66],"these":[67],"internal":[68,124],"nodes":[69,104],"therefore":[71],"cannot":[72],"be":[73,130],"ignored.":[74,92],"Also,":[75],"due":[76],"potentially":[79],"complex":[80],"feedback":[83,90,139],"bridges,":[84],"many":[85],"defects":[86],"that":[87,141],"cause":[88],"structural":[89],"are":[91],"We":[93,132],"propose":[94],"methodology":[96],"create":[98],"mapping":[100],"between":[101],"logic":[111],"level.":[112],"By":[113],"identifying":[114],"appropriate":[115],"activation":[117],"error":[119],"propagation":[120],"conditions":[121],"each":[123],"node,":[125],"accurate":[126],"can":[129],"formulated.":[131],"also":[133],"describe":[134],"strategy":[136],"modeling":[138],"bridges":[140],"enables":[142],"use":[144],"tools.":[148]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}